Method and apparatus for testing very large scale integrated mem

Details Method and apparatus for testing very large scale integrated mem Method and apparatus for testing very large scale integrated mem

1984-03-30

1986-07-15

Fleming, Michael R.

Excavating

371 21, G01R 3128

Patent

active

046010343

ABSTRACT:
Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at least some of them by the bit line connections. The parallel signature analyzer is configurable to apply selected signals onto the bit lines in one mode to enable test signals to be written into selected memory cells to generate preselected memory states therewithin. The parallel signature analyzer is also configurable, in another mode to read the states of the memory cells and to develop a signature of the states read to indicate whether the selectively applied signals were properly written into and read from the high density memory. Means are also provided for delivering the signature to an output lead in the form of a quotient bit, if desired.

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