Method and apparatus for testing the reliability of semiconducto

Details Method and apparatus for testing the reliability of semiconducto Method and apparatus for testing the reliability of semiconducto

1993-10-22

1995-05-09

Wieder, Kenneth A.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

3241581, G01R 104

Patent

active

054143519

ABSTRACT:
A method is described for testing the reliability of terminals in a semiconductor package proposes the placing of a test chip in the package, wherein the test chip has an insulating substrate, a conductive metal blanket layer on the substrate, a passivating layer over the metal layer provided with a plurality of openings, a plurality of Gold (Au) terminals in the openings bonded to the metal layer, and a master ground terminal bonded to the metal layer. Input/Output (I/O) terminals are provided in the package structure for each of the Au terminals, and master terminals are connected to the I/O terminals with wire, the test chip is sealed in the package. The resistance of each of the terminals is then monitored over a period of time to determine any change of electrical resistance, which is indicative of terminal deterioration. The package can be subjected to various stresses during the monitoring, to obtain a correlation between terminal deterioration under mechanical or electrical stress over a time interval.

REFERENCES:
patent: 4004449 (1977-01-01), Gorey et al.
patent: 4465973 (1984-08-01), Countryman, Jr.
"Wafer Level Joule-Heated J-Constant BM Tests", 1992 WRL Final Report, pp. 176-197.
"Characteristics of a Surface Conductivity Moisture Monitor for Hermetic Integrated Circuit Packages", in CH 1425 8/179/0000-0097, C 1979 IEEE pp. 97-100.

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