Method and apparatus for testing the address system of a memory

Details Method and apparatus for testing the address system of a memory Method and apparatus for testing the address system of a memory

1996-09-30

1997-11-18

Canney, Vincent P.

Excavating

371 211, G06F 1100

Patent

active

056895143

ABSTRACT:
A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.

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