Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-08
2004-12-21
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06833721
ABSTRACT:
This application claims priority from Korean patent application No. P2000-020653 filed Apr. 19, 2000 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to test technology for semiconductor devices, and more particularly to a method and apparatus for testing semiconductor devices using an actual board-type product.
2. Description of the Related Art
FIG. 1
illustrates a conventional process for fabricating and testing semiconductor integrated circuit devices and the printed circuit boards onto which they are typically assembled. First, numerous semiconductor devices are fabricated on a semiconductor wafer
10
. The semiconductor devices are then tested during a wafer-level test, and faulty devices are marked so that they can be sorted and disposed of after they are separated from the wafer during a wafer separation process.
Next, the semiconductor devices that pass the wafer-level test are assembled into packages. The packaged devices
20
are then tested for reliability using a burn-in test, which screens for early defects under extreme temperature and electrical conditions, and a functional test, which tests the electrical characteristics of the devices. Packaged devices that fail either of these tests are disposed of, and the remaining devices are either assembled into printed circuit board products (such as the memory module
30
shown in FIG.
1
), or they are sold to other manufacturers who assemble them into their own board-type products. The board-type products are then tested again after assembly.
A problem with the conventional test process described above is that the test conditions are not the same as the actual operating conditions that the semiconductor devices encounter during actual use. Therefore, even if a semiconductor device passes the burn-in and functional tests, it might still have a defect that cannot be detected until after it is assembled into a board-type product. This increases product costs due to the expense associated with repairing and retesting boards, and the waste associated with boards that cannot be repaired. For example, semiconductor memory devices are typically assembled onto board-type memory modules such as Single Inline Memory Modules (SIMMs) or Dual Inline Memory Modules (DIMMs) which contain numerous memory devices. The modules are then mounted to a piece of equipment such as a computer mother board through a board-edge connector. If the module contains a single memory device that fails to operate properly when the module is installed on an actual mother board, the entire module must typically be disposed of because it is expensive to remove and replace one of the memory devices, which are soldered onto the module.
Moreover, even if a defective semiconductor device operates properly when initially assembled into a board-type product, it might malfunction long after it has been shipped from the manufacturer when it is subjected to different operating conditions. This further increases product costs due to warranty returns and replacements and results in a loss of consumer confidence.
A further problem with the prior art test process described above is that conventional test equipment is complicated, bulky and expensive. For example, semiconductor memory device manufacturers typically utilize integrated circuit testers such as the Hewlett Packard model HP83000 tester and the Advan tester to test memory devices after they have been assembled into packages. These testers generate test signal patterns that simulate memory bus signals (e.g., clock, row address strobe (RAS), column address strobe (CAS), data, and address signals) that a memory device would receive from a central processing unit (CPU) or chipset when utilized in a board level device. The test signals are applied to the terminal leads of the memory device under test (DUT), and the tester analyzes the signals received back from the memory device to determine if the electrical characteristics are acceptable. This type of tester is capital-intensive and takes up floor space that would be better utilized for fabrication equipment. Although this type of tester is very flexible and can be programmed to test a wide range of device characteristics, it cannot provide an environment identical to that encountered during actual operation. Moreover, to provide this flexibility, the tester must necessarily be complicated, and therefore, difficult and expensive to program and operate.
SUMMARY OF THE INVENTION
One aspect of the present invention is a test board for testing semiconductor devices comprising a circuit board having a mounting unit for mounting a semiconductor device to the board and a connector for coupling the test board to a board-type product. An interface circuit on the test board couples the mounting unit to the board-type product and compensates for environmental differences between the board-type product and the mounting unit.
Another aspect of the present invention is a test board for testing semiconductor devices comprising a circuit board having a mounting unit for mounting a semiconductor device to the board and a connector for coupling the test board to a board-type product. A power control circuit manipulates the power supply provided to the semiconductor device.
A further aspect of the present invention is a system for testing semiconductor devices comprising a board-type product and a test board which can be coupled to the board-type product. The test board includes a mounting unit for mounting a semiconductor device to the test board which couples signals from the board-type product to the semiconductor device to allow the device to be tested under actual operating conditions.
Another aspect of the present invention is a method for testing semiconductor devices by coupling a test board to a board-type product, mounting a semiconductor device on the test board, and testing the semiconductor device by operating the board-type product.
REFERENCES:
patent: 4906987 (1990-03-01), Venaleck et al.
patent: 5794175 (1998-08-01), Conner
patent: 5966021 (1999-10-01), Eliashberg et al.
patent: 6505317 (2003-01-01), Smith et al.
patent: 2000-49650 (2000-08-01), None
patent: 2001-96955 (2001-11-01), None
English language of abstract for Korean Patent Publication No. 2000-49650, filed Aug. 5, 2000.
English language of abstract for Korean Patent Publication No. 2001-96955, filed Nov. 8, 2000.
Jeong Nam-Sik
Kim Chang-Nyun
Kim Jong-Hyun
Park Hyun-Ho
Park Sang-Jun
Marger & Johnson & McCollom, P.C.
Tang Minh N.
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