Method and apparatus for testing pin isolation for an integrated

Details Method and apparatus for testing pin isolation for an integrated Method and apparatus for testing pin isolation for an integrated

1995-01-30

1996-10-01

Trammell, James P.

Boots, shoes, and leggings

371 221, G05B 2302

Patent

active

055616143

ABSTRACT:
A low power mode of an integrated circuit (IC) 10 is tested via a test controller 50. The IC 10 is placed in a low power mode where a plurality of pins represented by the pins 82, 72, and 62 are isolated from the internal circuitry, such as CPU 30, via circuits 60, 70, and 80. It is difficult, if not impossible, to test the IC 10 when in a low power mode since all pins are isolated from external circuitry and all clocks are stopped. Therefore, in order to test the low power mode, the test controller 50 can be selectively taken-out of low power mode via a RESET IN signal while all other circuitry in the IC 10 remains in the isolated low power mode. Test controller 50 can then conduct logical low power internal testing of the IC 10 while it is in low power mode and isolated. This testing in done by communicating data via the DATA IN and DATA OUT pins in a serial scan chain manner.

REFERENCES:
patent: 5377200 (1994-12-01), Pedneau

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