Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
1998-09-11
2001-02-13
Lee, John R. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140RC, C348S294000
Reexamination Certificate
active
06188057
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the testing of photo-receiver arrays and associated read channels, and more particularly, to the testing of photo-receiver arrays and associated read channels which are constructed within a single integrated circuit.
BACKGROUND OF THE INVENTION
An accurate determination of the path of a device across a surface is important in a variety of applications. For example, in the field of optical scanners, there must be accurate information as to the travel of the scanning device along the original so that a faithful representation of an image of a scanned original may be acquired. Typically, the captured image provided by a scanner is a pixel data array that is stored in memory in a digital format. A distortion-free image requires a faithful mapping of the original image to the pixel data array.
Information as to the travel of a scanning device along an original may be obtained by an optical navigation system comprising a photo-receiver array. Optical navigation systems utilizing primarily analog-based technology are known in the art. For example, optical navigation systems comprising a photo-receiver array, an analog spatial image enhancement filter, and an analog correlator with off-chip bias and control are known. While usable, the accuracy of such analog systems is not optimal since so much of the algorithmic processing of the image signal (e.g., filtration, correlation) is done in the analog domain. The complementary metal oxide silicon (CMOS) technology supporting chips performing this processing cause slight imperfections and variations in the physical CMOS structure (e.g., non-linearity, device mismatches, power supply issues), to substantially affect a predictable and repeatable performance of such analog systems. As a result, analog optical navigation systems are not very suitable for mass manufacture.
Digital optical navigation systems, such as the one disclosed in U.S. patent application Ser. No. 09/040,640 of Badyal et al. filed Mar. 18, 1998, entitled “CMOS Digital Optical Navigation Chip”, have therefore been developed to overcome the disadvantages of analog optical navigation systems. Badyal discloses a CMOS digital integrated circuit (IC) chip on which an image is captured, digitized, and then processed on-chip in substantially the digital domain. A preferred embodiment of the IC disclosed by Badyal comprises imaging circuitry including a photo-receiver array for capturing an image and a charge transfer stage for generating a representative analog signal, conversion circuitry including an n-bit successive approximation register (SAR) analog-to-digital converter for converting the analog signal to a corresponding digital signal, filter circuitry including a spatial filter for edge and contrast enhancement of the corresponding image, compression circuitry for reducing the digital signal storage needs, correlation circuitry for processing the digital signal to generate result surface on which a minima resides representing a best fit image displacement between the captured image and previous images, interpolation circuitry for mapping the result surface into x-and y-coordinates, and an interface with a device using the chip, such as a hand-held scanner. The filter circuitry, the compression circuitry, the correlation circuitry and the interpolation circuitry are all advantageously embodied in an on-chip digital signal processor (DSP). The DSP embodiment allows precise algorithmic processing of the digitized signal with almost infinite hold time, depending on storage capability. The corresponding mathematical computations are thus no longer subject to the vagaries of a CMOS chip structure processing analog signals. As a result, precise and accurate navigation enables a predictable, reliable and manufacturable design. Parameters may also be programmed into the DSP's “software,” making the chip tunable, as well as flexible and adaptable for different applications.
A preferred embodiment of a photo-receiver in the photo-receiver array disclosed by Badyal et al. is further described in U.S. Pat. No. 5,769,384 of Baumgartner et al. issued June 23, 1998, entitled “Low Differential Light Level Photoreceptors”, and in U.S. patent application Ser. No. 09/024,092 of Knee et al. filed Feb. 17, 1998, now U.S. Pat. No. 6,104,020, entitled “Electronic Shutter for a Low Differential Light Level Photo-Receiver Cell”. Operation of the photo-receivers described in Baumgartner et al. and Knee et al. is further described in U.S. Pat. No. 5,149,980 of Ertel et al. issued Sep. 22, 1992, entitled “Substrate Advance Measurement System Using Cross-correlation of Light Sensor Array Signals”.
The above disclosed patents of Baumgartner et al. and Ertel et al., as well as the patent applications of Badyal et al. and Knee et al., are hereby incorporated by reference for all that they disclose.
SUMMARY OF THE INVENTION
A problem with constructing photo-receiver arrays and their associated read channels on a single IC is that it becomes difficult to adequately test the photo-receiver arrays and their read channels.
One method of testing these elements is by observing IDDQ currents (quiescent current draws) for the entire chip. A global test such as this will show if a device is shorted, or if large numbers of photoelements are not biased properly. However, it will not show if random pixels are dead. Optical testing has historically been done after packaging.
As array sizes grow and packaging costs rise, it is desirable to identify photo-receiver arrays with defects before they are packaged. The inventor has therefore devised methods and apparatus which enable the testing of photo-receiver arrays and their associated read channels either prior to, or after, they are packaged in an integrated circuit.
In summary, testing may be accomplished by injecting analog test voltages into 1) a multiplexor stage preceding a charge transfer stage, and 2) multiplexors preceding a number of analog-to-digital converters. In this manner, the analog-to-digital converters may be isolated from the charge transfer stage while test voltages are injected to the analog-to-digital converters. After proper operation of the analog-to-digital converters has been verified, additional test voltages may be used to write charges to integration capacitors of photo-receivers in a photo-receiver array. These charges may then be read out through the same multiplexors which were used to write them to the integration capacitors. When combined with illumination and shutter control of the photo-receivers, the write of test charges to the integration capacitors may be used to fully exercise and test the elements of a photo-receiver array and its read channels.
Utilizing the methods and apparatus disclosed herein, photo-receiver arrays and their read channels may be tested prior to the packaging of an IC such as an optical navigation IC. Next higher assembly costs may thereby be avoided if a photo-receiver array and/or its read channels is determined to be bad.
These and other important advantages and objectives of the present invention will be further explained in, or will become apparent from, the accompanying description, drawings and claims.
REFERENCES:
patent: 5149980 (1992-09-01), Ertel et al.
patent: 5451768 (1995-09-01), Hosier et al.
patent: 5769384 (1998-06-01), Baumgartner et al.
patent: 6078358 (2000-06-01), Bird
patent: 6104020 (2000-08-01), Knee et al.
U.S. Patent Application Ser. No. 09/040,640 of Badyal et al. filed Mar. 18, 1998, entitled “CMOS Digital Optical Navigation Chip”.
U.S. Patent Application Ser. No. 09/024,092 of Knee et al. filed Feb. 17, 1998, entitled “Electronic Shutter for a Low Differential Light Level Photo-Receiver Cell”.
Agilent Technologie,s Inc.
Lee John R.
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