Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1997-10-23
1999-10-12
Ballato, Josie
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
G01R 3126
Patent
active
059660252
ABSTRACT:
A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as an address lead unused during testing, redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled through a switching transistor to a common cell plate or DVC2 node for all storage capacitors in the memory circuit. External power can thereby be provided to the DVC2 node to simultaneously apply a high voltage to this node of all capacitors during stress testing of the chip. The arrangement allows for efficient testing for dielectric defects in the capacitors while the die is in packaged chip form.
REFERENCES:
patent: 4573146 (1986-02-01), Graham et al.
patent: 4595875 (1986-06-01), Chan et al.
patent: 4769784 (1988-09-01), Doluca et al.
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5212442 (1993-05-01), O'Toole et al.
patent: 5257229 (1993-10-01), McClure et al.
patent: 5291454 (1994-03-01), Yamasaki et al.
patent: 5291455 (1994-03-01), Feng et al.
patent: 5297099 (1994-03-01), Bolan et al.
patent: 5307318 (1994-04-01), Nemoto
patent: 5317532 (1994-05-01), Ochii
patent: 5355340 (1994-10-01), Coker et al.
patent: 5381373 (1995-01-01), Ohsawa
patent: 5434438 (1995-07-01), Kuo
patent: 5466888 (1995-11-01), Beng et al.
patent: 5467356 (1995-11-01), Choi
patent: 5473198 (1995-12-01), Hagiya et al.
patent: 5511029 (1996-04-01), Sawada et al.
patent: 5535161 (1996-07-01), Kato
patent: 5544106 (1996-08-01), Koike
patent: 5559741 (1996-09-01), Sobue
patent: 5563832 (1996-10-01), Kagami
patent: 5590075 (1996-12-01), Mazzali
patent: 5608337 (1997-03-01), Hendricks et al.
patent: 5619462 (1997-04-01), McClure
patent: 5627478 (1997-05-01), Habersetzer et al.
patent: 5648730 (1997-07-01), Bhuva et al.
patent: 5652725 (1997-07-01), Suma et al.
patent: 5777932 (1998-07-01), Chonan
Ballato Josie
Kobert Russell M.
Micro)n Technology, Inc.
LandOfFree
Method and apparatus for testing of dielectric defects in a pack does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing of dielectric defects in a pack, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing of dielectric defects in a pack will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-656105