Method and apparatus for testing memory

Details Method and apparatus for testing memory Method and apparatus for testing memory

1990-02-14

1991-12-17

Smith, Jerry

Excavating

371 211, G11C 2900

Patent

active

050738917

ABSTRACT:
A method and apparatus for testing the integrity of a memory storing controlled information. The data array semiconductor memory that stores controlled information such as instructions or microcodes, is partitioned into two halves. One half stores the test pattern information, the other half stores the test program. An instruction test (I-TEST) instruction is provided for testing the instruction cache data array. The test program comprises a pair of I-TEST instruction and checkerboard pattern forming an instruction equivalent to the width of the data array. The I-TEST instruction runs in dual instruction mode with a floating point instruction replaced by the test pattern. The I-TEST program is executed by transferring its test pattern data from the instruction cache data array to a register R1 in the register file, and then comparing that data with the expected value located in a register other than R1 in the register file. If any comparison fails, then a defect in the data array will have been detected. To fully cover the data array, the I-TEST program must be repeated with test patterns located in the other half of the data array and swapped by a swapper which is coupled to the data array. The swapping action is accomplished by simply aligning the I-TEST instruction on the odd eight-byte boundaries rather than the even byte boundary.

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Smith, Alan J., Cache Memories, Computing Surveys, vol. 14, No. 3, pp. 473-530 (Sep. 1982).

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