Method and apparatus for testing long counters

Details Method and apparatus for testing long counters Method and apparatus for testing long counters

1995-01-26

1996-01-02

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

H03K 2140

Patent

active

054815800

ABSTRACT:
An n-bit counter (18) (where n is an integer.gtoreq.1) may be tested by first reconfiguring the counter during a test mode to generate successive first and second half-counts when the counter is successively clocked. During the test mode, a logical equality comparator (70) compares the half-counts to each other. When the half-counts are unequal (signifying a counter fault), the counter is inhibited from further counting. In this way, the counter is advantageously frozen at the faulty value. When the counter is inhibited from counting, its carry bit (CO) no longer toggles. Thus, by examining the counter carry bit, an indication can be had whether the counter is operating properly during the test mode.

REFERENCES:
patent: 3613014 (1971-10-01), Moegen
patent: 4336448 (1982-06-01), Shipp et al.
patent: 4373201 (1983-02-01), Bohan
patent: 4745630 (1988-05-01), Underwood
patent: 4860325 (1989-08-01), Aria et al.
patent: 4979193 (1990-12-01), Mehta
patent: 4991185 (1991-02-01), Hatten et al.
patent: 5339343 (1994-08-01), Hashimoto
patent: 5381453 (1995-01-01), Chan

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