Method and apparatus for testing large embedded counters

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation

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377 54, H03K 2140

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active

054736510

ABSTRACT:
An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means. Thus, during the one phase, the first section functions as a timer for the second section and during the second phase, the second section functions as a timer for the first section. The counts generated by the first and second sections are subsequently totalled and compared with a predetermined number to ascertain the operability of the counter.

REFERENCES:
patent: 3613014 (1971-10-01), Moegen
patent: 4336448 (1982-06-01), Shipp et al.
patent: 4519090 (1985-05-01), Stackhouse et al.
patent: 4860325 (1989-08-01), Aria et al.
patent: 5381453 (1995-01-01), Chan

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