Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2002-06-20
2004-06-29
Wachsman, Hal D (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S125000, C702S120000, C324S765010
Reexamination Certificate
active
06757632
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior European Patent Application No. 01-830417.0, filed Jun. 21, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit testing and measurement, and more specifically to the testing and measurement of integrated circuits in an automated test environment.
2. Description of Related Art
Testing and measurement is an important phase in integrated circuit design and manufacturing. Albeit the specific tests and measurements to be conducted vary greatly depending on the type of integrated circuit and the function or functions it is intended to perform, it is in general necessary to check for the absence of faults and the compliance of the circuit with the desired specifications. To do this, a relatively high number of measurements in several operating conditions is conducted.
Normally this is done in an Automatic Test Environment (“ATE”), programmed to perform several measurements in different operating conditions on specified electrical quantities, which are useful to provide a characterization of the integrated circuit, by means of a sampler instrumentation.
A large number of acquisitions by the sampler instrumentation is required. Generally stated, each acquisition is made up of five steps. A first step provides for setting up all the instruments involved in the measurement A second step provides for setting the test conditions for the integrated circuit to be tested. In a third step the sampler instrumentation performs the actual acquisition (i.e., it samples the specified electrical quantities so as to measure the integrated circuit response to the set test conditions). In a fourth step mathematical calculations are performed on the acquired data. In a fifth step all the instruments are reset.
Clearly, the test time rapidly increases with the number of acquisitions to be performed, that is with the number of different test condition setups. Up to now, two techniques have been followed in order to perform these kind of measurements.
A first technique, illustrated by a flowchart in
FIG. 1
, can be referred to as “multi-acquisition”. According to this technique, all five steps outlined above have to be repeated for each measurement to be conducted on the integrated circuit, that is for each test condition setup. Referring to
FIG. 1
, after all the instruments involved in the measurement have been set up (block
11
, “STUP INSTR”), an analog time acquisition routine (sampling routine) is started (block
12
, “T ACQ STRT”). The integrated circuit under test is then put in a prescribed test condition setup (block
13
, “SET COND”). Such test condition setup is chosen from a set of test condition setups corresponding to several tests to be conducted on the integrated circuit. During the sampling routine the sampler instrumentation samples the specified integrated circuit characteristic quantities so as to acquire the response of the integrated circuit to the programmed test condition setup (block
14
, “MEAS”). Once the integrated circuit response has been acquired, the analog time acquisition routine is stopped (block
15
, “T ACQ STOP”). Mathematical calculations are then performed on the acquired data (block
16
, “MTH CALC”) and finally the measurement instruments are reset (block
17
, “RST INSTR”).
The above steps are repeated until all the test condition setups have been implemented (block
18
, “LST?”).
The advantage of the multi-acquisition technique resides in its ease of implementation and in the possibility of predicting the overall test time given a set of test condition setups. However, this technique is inherently time consuming, due to the need for repeating the five steps for each test condition setup. Considering that each chip of the integrated circuit coming out from manufacturing has to be tested, the time needed to perform the integrated circuit testing and measurement severely impacts the overall production cost, especially in large scale production.
A second technique, illustrated by the flowchart of
FIG. 2
, can be defined as “single acquisition”. According to this technique, the sampler instrumentation is started at the beginning of the testing and measurement program to start the acquisition. All the test condition setups are then sequentially implemented. The sampler instrumentation is stopped when all the test condition setups have been implemented. Referring to
FIG. 2
, after all the instruments involved in the measurement have been set up (block
21
, “STUP INSTR”), an analog time acquisition routine (sampling routine) is started (block
22
, “T ACQ STRT”). The integrated circuit is then put in a prescribed test condition setup (block
23
, “SET COND”). Again, such test condition setup is chosen from a set of test condition setups corresponding to several tests to be conducted on the integrated circuit. The sampler instrumentation samples the characteristic quantities of the integrated circuit so as to acquire the response of the integrated circuit to the test condition setup (block
24
, “MEAS”). The operations corresponding to blocks
23
and
24
are repeated until all the test condition setups have been implemented (block
25
, “LST?”).
Once the integrated circuit response to all the test condition setups has been acquired, the analog time acquisition routine is stopped (block
26
, “T ACQ STOP”). Mathematical calculations are then performed on the acquired data (block
27
, “MTH CALC”) and finally the instruments are reset (block
28
, “RST INSTR”).
Compared to the multi-acquisition technique, the single acquisition technique has the advantage of saving time, because the starting and stopping of the sampling routine, the setting up of the instruments involved in the measurement and the mathematical calculations have to be performed only once.
However, it has been observed that this technique also has some drawbacks. The drawbacks of this technique reside in the instability in time acquisition, since the time of absence of signal on the quantities under measure (i.e., the time during the switch between different test condition setups) varies when switching between different pairs of test condition setups. For example,
FIG. 3
is a diagram showing the response R (in mV) of an integrated circuit to six different test condition setups, for instance the response R on six different channels CH
1
-CH
6
of a programmable Radio-Frequency (RF) integrated circuit having several different channels which all must be tested. The abscissa represents the number of samples S acquired by the sampler instrumentation. As shown, the time of absence of signal differs when switching between different pairs of channels. It is therefore difficult, if not impossible, to determine whether the sampled data relate to an effective integrated circuit response to a given test condition setup, or to a time interval between two different test condition setups. This problem becomes more and more significant with the increase in the number of different test conditions to be implemented.
Another negative consequence of this problem is the unpredictability of the time needed to complete the test program.
Additionally, it has been observed that the repeatability of the measurement between successive runs of the test program on the same integrated circuit is scarce. This is for example shown in
FIGS. 4A and 4B
which, similarly to
FIG. 3
, show the response R, in two successive runs of the test program, of six different channels CH
1
-CH
6
of a programmable Radio-Frequency (RF) integrated circuit having several different channels which all must be tested.
SUMMARY OF THE INVENTION
In view of the state of the art, it is an object of the present invention to provide a method for testing integrated circuits that is not affected by the drawbacks of conventional testing and measurement techniques.
One embodiment of the present invention provides a method for testing an integrated circuit in an automatic test environment. A
Di Gregorio Giuseppe
Russo Biagio
Tuttobene Giuseppe
Bongini Stephen
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Jorgenson Lisa K.
STMicroelectronics S.r.L.
Wachsman Hal D
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