Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2006-07-27
2009-06-23
Hollington, Jermele M (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
07550990
ABSTRACT:
In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.
REFERENCES:
patent: 5326994 (1994-07-01), Giebel et al.
patent: 5430595 (1995-07-01), Wagner et al.
patent: 5541547 (1996-07-01), Lam
patent: 5825600 (1998-10-01), Watt
patent: 6469538 (2002-10-01), Gupta
patent: 6479871 (2002-11-01), Peters et al.
patent: 6493850 (2002-12-01), Venugopal et al.
patent: 6553542 (2003-04-01), Ramaswamy et al.
patent: 6636067 (2003-10-01), Salcedo-Suner
patent: 6858902 (2005-02-01), Salling et al.
patent: 6985002 (2006-01-01), Salcedo
patent: 2006/0050453 (2006-03-01), Duvvury et al.
patent: 2006/0215337 (2006-09-01), Wu et al.
patent: 2007/0090392 (2007-04-01), Boselli
De Manari I et al: “A Test Pattern for Three-Dimensional Latch-Up Analysis”; Microelectronic Test Structures 1993 ICMTS 1993; Proceeedings of the 1993 International Conference on SITGES, Spain Mar. 22-25, 1993; N.Y. USA; IEEE US Mar. 22 1993; pp. 103-109.
Munari De et al: “Design and Simulation of a Test Pattern for Three-Dimensional Latch-Up Analysis”; Microelectronics Journal Mackintosh Publications LTD; Luton GB; vol. 24, No. 7; Nov. 1, 1993; pp. 759-771.
Cappon Paul H.
De Jong Peter C.
Scarpa Andrea
Smedes Taede
Hollington Jermele M
NXP B.V.
Zawilski Peter
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