Method and apparatus for testing integrated circuits

Details Method and apparatus for testing integrated circuits Method and apparatus for testing integrated circuits

1992-08-11

1996-02-27

Voeltz, Emanuel T.

Excavating

371 211, 371 225, H04B 1700, G11C 2900

Patent

active

054954860

ABSTRACT:
Individual elements of an integrated circuit such as storage elements, (for example, latch elements), can be selectively coupled to select lines and probe lines. During normal operation the latches are not connected to the select lines and behave as a normal latch. During a write/control test operation, the latch is connected to a select line and data placed on the select line is provided to an input of latch. Thereafter, the latch is placed into a latching state in response to the probe line and the clock signal, latching the data provided from the select line into latch. In order to read/observe data, the clock line and probe line are controlled to route data onto the associated select line. In one embodiment the probe line controls a transistor switch that connects the select line to the input of the latch. The probe line also controls a transmission gate which is placed in the latch to toggle the latch between a latching condition and a non-latching condition, in response to signals on the probe line. Preferably each select line and probe line are attached to a plurality of elements and each element is connected to one select line and one probe line. Thus, by placing signals on the select line and probe line, any individual IC element can be addressed for controlling and/or observing.

REFERENCES:
patent: 3806891 (1974-04-01), Eichelberger
patent: 4429388 (1984-01-01), Fukushima et al.
patent: 4498172 (1985-02-01), Bhavsar
patent: 4613970 (1986-09-01), Masuda et al.
patent: 4739250 (1988-04-01), Tanizawa
patent: 4749947 (1988-06-01), Gheewala
patent: 4757503 (1988-07-01), Hayes et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5032783 (1991-07-01), Hwang et al.
patent: 5065090 (1991-11-01), Ghewala
patent: 5122738 (1992-06-01), Simpson et al.
patent: 5206862 (1993-04-01), Chandra et al.
patent: 5231345 (1993-07-01), Katakura et al.
patent: 5255227 (1993-10-01), Haeffele
patent: 5258986 (1993-11-01), Zerbe
patent: 5289475 (1994-02-01), Slemmer
"Built-In Self-Test Techniques", pp. 21-28, IEEE Design & Test, Apr. 1985.
"Using Scan Technology For Debug and Diagnostics In A Workstation Environment", pp. 976-986, International Test Conference, 1988.
"ATPG Based On A Novel Grid-Addressable Latch Element", pp. 282-286, ACM/IEEE Design Automation Conference, 1991.
"Microelectronic Circuits", pp. 884 and 885, Holt, Rinehart and Winston, Inc.

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