Method and apparatus for testing integrated circuit memories

Details Method and apparatus for testing integrated circuit memories Method and apparatus for testing integrated circuit memories

1988-08-05

1990-10-23

Smith, Jerry

Excavating

371 213, 371 27, G06F 1100

Patent

active

049657992

ABSTRACT:
A method and apparatus for testing the functionality and maximum operating speed of a dynamic random access memory (DRAM) chip includes a random sequencer circuit for generating a pseudo-random data bit pattern to be written into the cells of a DRAM chip. The apparatus includes a variable clock circuit which produces a continuously variable frequency clock signal to continuously increase the speed at which data is written into the DRAM. During read cycles of the DRAM, data read from the DRAM is compared with the pattern produced by the random sequencer in a comparator, and any non-correspondence between bits will activate an LED to indicate a failure of the chip. In this way, the maximum speed of the chip may be determined to isolate both defective and marginally damaged chips. The apparatus is operated as a stand-alone unit which does not require the use of any software or interfaced host microprocessor.

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