Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1997-06-27
2000-10-24
Brown, Glenn W.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324754, 324760, 324765, G01R 3126, G01R 1067
Patent
active
061372994
ABSTRACT:
Formation of a contact probe having a pattern of dendritic textured contacts complementary to that of a contact pad array on a bare chip allows formation of simultaneous temporary connections to all contact pads of the bare chip at a much reduced compressional force across the chip. The reliability of such connections at such a reduced force allows screening, burn-in and full functional testing of the bare chip at a high throughput by an automated apparatus to exploit potential economies of "known good die" (KGD) processing for limiting or avoiding repair, rework and further processing of less than fully functional chips for complex electronic packages. The compressional force is sensed by a pressure sensor, the output of which controls the advancement of the bare chip toward the contact probe such that the dendritic textured contacts of the contact probe penetrate the contact pads of the bare chip.
REFERENCES:
patent: 4103814 (1978-08-01), Nishioka
patent: 4135630 (1979-01-01), Snyder et al.
patent: 4160893 (1979-07-01), Meyen et al.
patent: 4673839 (1987-06-01), Veenendaal
patent: 4799854 (1989-01-01), Niskala
patent: 4912399 (1990-03-01), Greub et al.
patent: 4995157 (1991-02-01), Hall
patent: 5040291 (1991-08-01), Janisiewicz et al.
patent: 5105537 (1992-04-01), Datta et al.
patent: 5118299 (1992-06-01), Burns et al.
patent: 5137461 (1992-08-01), Bindra et al.
patent: 5163834 (1992-11-01), Chapin et al.
patent: 5230632 (1993-07-01), Baumberger et al.
patent: 5237743 (1993-08-01), Busacco et al.
patent: 5313157 (1994-05-01), Pasiecznik, Jr.
patent: 5406210 (1995-04-01), Pedder
patent: 5414372 (1995-05-01), Levy
patent: 5420520 (1995-05-01), Anschel et al.
patent: 5469072 (1995-11-01), Williams et al.
patent: 5475317 (1995-12-01), Smith
patent: 5497103 (1996-03-01), Ebert et al.
patent: 5517125 (1996-05-01), Posedel et al.
patent: 5521522 (1996-05-01), Abe et al.
patent: 5523696 (1996-06-01), Charlton et al.
patent: 5550482 (1996-08-01), Sano
patent: 5559446 (1996-09-01), Sano
patent: 5570032 (1996-10-01), Atkins et al.
patent: 5604446 (1997-02-01), Sano
patent: 5633122 (1997-05-01), Tuttle
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5796264 (1998-08-01), Farnworth et al.
patent: 5818247 (1998-10-01), Pyun
patent: 5880590 (1999-03-01), Desai et al.
Cadieux Robert R.
Correia George C.
Hill Gary R.
Ingraham Anthonty P.
Brown Glenn W.
International Business Machines - Corporation
Leas, Esq. James M.
Woods McGuire
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