Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-03-30
2002-12-03
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C324S762010
Reexamination Certificate
active
06489798
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to image sensing circuits arrays, and more particularly to the method and apparatus for testing the arrays.
BACKGROUND OF THE INVENTION
A conventional sensing array is composed of individual light sensitive circuits called pixels that are organized in rows and columns. A row of pixels has a common line connecting the control gates of their respective access transistors. Data is passed from a pixel through its access transistor to a data line. Each column of pixels is connected to a common data line. During the manufacture of a sensor array, open or short circuits may occur between adjacent row lines or adjacent data lines due to the presence of dust or other particulate matter. Open or short circuiting of row lines or data lines may also occur due to improper control of the etching process.
CMOS image sensor arrays can employ several types of pixels. Passive pixel sensor circuits are comprised of a simple photodiode and an access transistor. Active pixel sensor (APS) circuits have added features including a reset transistor and a source follower amplifier. Individual sensor circuits may suffer from similar problems as the row lines and data lines, in that they may be either short circuited or open circuited and therefore do not perform their proper function. In order to overcome these problems, defects in the sensor array must be detected in order to select arrays that are acceptable for use.
Integrated image sensors have traditionally been relatively expensive devices, many of which used a technology known as charge coupled device (CCD). The nature of these devices did not permit the use of extensive integrated test features, therefore testing was primarily dependent on the use of external light sources. This traditional test method continued for the testing of CMOS image sensors such as those using APS circuits. Therefore, testing of integrated imager active pixel sensor arrays has required the use of expensive, calibrated light sources to perform optical testing of the sensors. Typically, during production testing, an image sensor would be exposed to light of varying intensity ranging from black to white. Measurements would be taken to determine the response of the array. The length of time required to perform these optical tests can be excessive, adding dramatically to the cost of the device. Reduction of test times and therefore costs can be accomplished by reducing the dependency of these tests on a calibrated light source.
In addition to the time required to test an integrated imager array using a calibrated light source, the accuracy of the test is also a concern. If two neighboring pixels were shorted together during the manufacturing process, the measured output would be the same as if the pixels were not shorted together. This occurs because both pixels have been exposed to the same intensity of light. The defect may go undetected until the device is placed in a system and tested under “real world” conditions. Unfortunately, detection of the defect is dependent on human viewing of the output as displayed on the viewing device (e.g. a cathode ray tube or liquid crystal display panel). As the number of pixels on an integrated circuit expands, it becomes increasingly difficult for a human to detect such faults. Special training is required for the human observers and even then, human interpretation plays a major role in the determination of acceptable products. However, humans lack consistent observational skills due to their very nature and varying levels of alertness throughout the day. Therefore, this type of testing is not acceptable for high volume, cost sensitive sensor products.
Other testing methods have been proposed. U.S. Pat. No. 5,276,400 which issued to Denyer et al on Jan. 4, 1994 discloses a test arrangement which does not require the irradiation of the array by a light source. Test circuitry is integrated at the periphery of the sensor array which attempts to drive digital test patterns on the row access lines and data lines. The resulting signal patterns can then be compared to expected values to determine the presence of production faults. This is a much faster test method than those mentioned previously. However, the arrangement proposed by Denyer et al has two major shortcomings. It is suited for passive pixel arrays but not for arrays of active pixel sensors. In an active pixel array, it would only allow for the testing of row line and data line integrity and not for the testing of the individual pixel structures. In addition, digital test patterns are used and these will not necessarily provide accurate results since during actual operation, the voltages obtained on the data lines are analog signals due to the nature of the sensor array.
Another test system is disclosed by U.S. Pat. No. 5,451,768 which issued to Hosier et al on Sep. 19, 1995. This system involves test circuitry integrated on the same die as the sensor array for testing a specific pixel and transfer circuit arrangement. This arrangement involves a circuit for injecting a certain amount of charge into the transfer circuit and a smaller amount of charge to bias the photodiode. The difference between these two charges is indicative of the linear response of the pixel. The test circuit places a known amount of bias charge into the pixel. The pixel is not illuminated during testing, so this bias charge should be shifted out through the transfer circuit. This allows testing for the presence of the correct bias charge and for the proper photodiode response linearity. However, this system does not account for the identification of problems with the row lines or data lines such as short circuits between adjacent lines or open circuits in an individual line.
U.S. Pat. No.5,654,537 which issued to Prater on Aug. 5, 1997 also proposes a system for testing an image scanner array having pixel sensor circuits arranged in rows and columns. Prater's apparatus includes a reset voltage source having selectable voltage that may vary in amplitude between ground and the supply voltage levels. The photo-sensitive devices in the pixel sensor circuits are cyclically tested using a different selected voltage for each cycle to reset the photosensitive devices in the pixel sensor circuits. During each cycle, the outputs of the pixel sensor circuits are sensed to determine whether they are functioning properly. By varying the reset voltage between ground and the power supply as disclosed by Prater, the pixel sensor circuits are tested as if they had received different illumination levels without the need for a calibrated light source. However, the system does not differentiate between adjacent pixel sensor circuits. Prater discloses supplying the variable reset voltage to the drain of the reset transistors in the pixel sensor circuits in the rows and columns. If two neighbouring pixels were shorted together, the measured output would be the same as if the pixels were not faulty because both pixels would have been reset to the same voltage.
Therefore, there is a need for a method and apparatus capable of testing individual radiation sensitive circuits in an image sensing array as well as the supply and control lines in the array.
SUMMARY OF THE INVENTION
The invention is directed to a method and apparatus for testing an image sensor array having sensor circuits arranged in rows and columns. The method includes resetting the voltage of the photosensitive device in each of the sensor circuits such that adjacent circuits are reset to different voltage levels, and then sensing the voltage on each of the reset photosensitive devices.
In accordance with one aspect of the invention, the voltage resetting step includes applying common reset voltages to sensor circuits in the columns such that adjacent columns receive different reset voltage amplitudes and applying common enable voltage signals to the sensor circuits in the rows such that adjacent rows receive different enable signal amplitudes.
In accordance with another aspect of this invention, the voltage
Chamberlain George
Little Tom
McDonald Ron
Scott-Thomas John
Hayes & Soloway PC
Patel Paresh
Symagery Microsystems Inc.
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