Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-05-31
2002-11-05
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
C327S156000
Reexamination Certificate
active
06476594
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to a method and apparatus for testing high frequency delay locked loops with low frequency production testers.
Delay-locked loops (DLLs) are used in integrated circuits, such as application specific integrated circuits (ASICs) for removing phase differences between clocks, such as phase differences caused by propagation delay. A typical DLL includes a phase detector, a charge pump, a loop filter and a voltage-controlled delay line. The phase detector detects a phase difference between a reference clock signal and a feedback clock signal. The phase detector generates a phase control signal as a function of the phase difference and applies the phase control signal to the charge pump, which increases or decreases a voltage across the loop filter. This voltage is applied to the voltage-controlled delay line for controlling the propagation delay through the delay line. The reference clock is fed through the delay line to generate an output clock, which is fed back to the phase detector as the feedback clock, typically through additional logic such as a binary clock tree. The delay line advances or retards the phase of the output clock until the phase of the feedback clock matches the phase of the reference clock. The DLL has then locked the output clock signal onto the phase of the reference input signal.
As with other types of logic in an integrated circuit, fabrication faults can effect the functionality of a DLL. Embedded DLLs are tested by applying a test clock signal to the reference input of the DLL and then measuring the resulting frequency at the clock output of the DLL. However, a DLL normally requires that the test clock signal be within the DLLs “locking range” in order to lock the output clock signal onto the phase of the test clock signal. As the operating frequencies of DLL's continue to increase, it is becoming more difficult for production test equipment to provide a DLL with a test clock signal that is within the locking range. For example, most production testers available today have a maximum frequency of 100 megahertz (MHz). However, a 500 MHz DLL would require a test clock signal having a frequency of about 500 MHz in order to lock. Modern VLSI production tester cannot provide a reference lock at 500 MHz. Even if these testers were modified to provide a 500 MHz reference clock signal, the cost of these testers would become prohibitive. As a result, high-speed DLLs are typically not tested with the other internal logic of an integrated circuit prior to packaging. Any functional problems associated with the DLL would therefore not be detected until after the integrated circuit has been packaged, which increases the expense associated with such faults.
An improved method of testing high-speed DLLs is therefore desired.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed to a delay-locked loop circuit which includes a delay-locked loop, a delay element and a multiplexer. The delay-locked loop has a reference clock input, a feedback clock input and a clock output. The delay element has a delay input which is coupled to the clock output and a delay output. The multiplexer has a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the delay output and a multiplexer output which is coupled to the feedback input.
Another aspect of the present invention is directed to a method of testing a delay-locked loop that is embedded within an integrated circuit. According to the method, a test clock is applied to a reference clock input of the delay-locked loop, wherein the test clock signal has a frequency that is outside a normal locking range of the delay-locked loop. The normal locking range of the delay-locked loop is lowered to a test locking range, wherein the frequency of the test clock signal is within the test locking range. A representation of an output clock signal generated by the delay-locked loop on a clock output of the delay-locked loop in response to the test clock signal is detected when the delay-locked loop has the test locking range.
Another aspect of the present invention is directed to an integrated circuit having an embedded delay-locked loop with a reference clock input, a feedback clock input, a test control input, a clock output and a feedback path from the clock output to the feedback clock input. The integrated circuit further includes a circuit for selectively changing a locking range of the delay-locked loop from a first frequency range to a second, slower frequency range as a function of a test control signal applied to the test control input.
REFERENCES:
patent: 5717353 (1998-02-01), Fujimoto
patent: 6285225 (2001-09-01), Chu et al.
patent: 6396889 (2002-05-01), Sunter et al.
Le N.
LSI Logic Corporation
Nguyen Vincent Q.
Westman Champlin & Kelly
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