Method and apparatus for testing electronic devices

Details Method and apparatus for testing electronic devices Method and apparatus for testing electronic devices

2000-05-09

2002-12-17

Sherry, Michael J. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S762010

Reexamination Certificate

active

06496028

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to electronic device testing via supply current monitoring.
BACKGROUND OF THE INVENTION
In recent years, it has been shown that some physical defects, which do not affect the logic behavior of an electronic circuit or device (for instance a CMOS device) usually cannot be detected using voltage oriented test techniques. However, they often apparently reduce the reliability of the circuit. No doubt that testing is best performed using a combination of test techniques, with each method dedicated to detect a class of defects. Quiescent power supply current monitoring has been used to detect a variety of such defects See S. McEUEN, “Reliability benefits of I
DDQ
”, Journal of Electronic Testing: Theory and Applications, Vol. 3, No. 4, December, 1992, pp. 41-49; W. Mao, R. K. Gulati, D. K. Goel and M. D. Cilleti, “QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults”, Proc. of Inter. Conf. on Computer Aided Design, 1990, pp. 280-283; C. F. Hawkins and J. M. Soden, “Electrical characteristics and testing consideration for gate oxide shorts in CMOS ICs”, Proc. of The 1985 Test Conf, Philadelphia, Pa., 1985, pp. 544-555; W. Maly and M. Patyra, “Built-in Current Testing”, IEEE Journal of Solid State Circuits, Vol. 27, No. 3, March 1992, pp. 425-428.
Nevertheless, the efficiency of Quiescent Current Testing for detecting open defects presents some limitations due to the fact that these failures may prevent changes of the quiescent power supply current. See C. L. Henderson, J. M. Soden and C. F. Hawkins, “The behavior and testing implications of CMOS IC logic gate open circuits”, Proc. of Inter. Test Conference, November, 1991, pp. 302-310; V. H. Champac, A. Rubio and J. Figueras, “Electrical model of the floating gate defect: Implications on I
DDQ
testing”, IEEE Trans., 1994, CAD-13 (3), pp. 359-369.
Therefore, the transient power supply current testing (IDDT testing) [S-T. Su and R. Z. Makki, “Testing of SRAMs by Monitoring Dynamic Power Supply Current”, JETTA, Vol. 3, 1992, pp. 265-278.][S-T. Su, R. Z. Makki and T. Nagle, “Transient Power Supply Current Monitoring—A New Test Method for CMOS VLSI Circuits”, JETTA, Vol. 6, February 1995, pp. 23-43.] can be conveniently used to augment the existing test methods and to enhance the defect coverage. On the other hand, the on-chip measurement of the dynamic current presents a more complex issue than performing I
DDQ
testing.
So far, only a few transient built-in current (BIC) monitors have been proposed See J. Segura, M. Roca, D. Mateo and A. Rubio, “Built-in dynamic current sensor circuit for digital VLSI CMOS testing”, Electronics Letters, Vol. 30, No. 20, Sept. 1994, pp. 1668-1669; J. Arguelles, M. Martinez, and S. Bracho, “Dynamic I
DD
test circuit for mixed-signal ICs”, Electronics Letters, Vol. 30, No. 6, March 1994, pp. 485-486; Y. Maidon, Y. Deval, J. B. Begueret, J. Tomas, and J. P. Dom, “3.3V CMOS Built-In Current Sensor”, Electronics Letters, Vol. 33, No. 5, February 1997, pp. 345-346.
In the state of the art, no current test monitors not influencing the operation of the DUT (Device Under Test) are available in the context of both static and dynamic (transient) currents and being either on-chip or off-chip.
The Philips Patent Application EP 0386804 A2 shows an arrangement for measuring the quiescent current of a digital circuit wherein the digital circuit under test is incorporated in the branches of a current mirror. Between the supply voltage and the voltage applied to said digital circuit under test an active element is found, resulting in a supplementary voltage drop, influencing the normal operation of the DUT.
The Texas Instruments Patent Application EP 0525421 A2 measures a voltage drop over a test object, and generates a voltage, being the voltage difference over two branches of a three branch current mirror. The connections of two branches of said three branch current mirror are made at an opposite side of the test object and are thus connected to another connection wire.
AIMS OF THE INVENTION
It is an aim of the invention to present an apparatus and methods for testing electronic devices via supply current measurements. Said apparatus and methods are not substantially influencing the normal operation of the electronic Device Under Test and can be implemented either on-chip or off-chip. Both static and dynamic (transient) currents are considered. Said devices can be digital, analog or mixed digital analog.
It is also an aim of the invention to present an apparatus and method wherein a fixed, non-time varying current is sent through a test object and thus influences the normal operation of the test object.
SUMMARY OF THE INVENTION
In a first aspect of the invention, a test device for testing an electronic device by measuring a supply current flowing in said electronic device is presented. Said supply current flows in a supply line from the powerline through the electronic device to ground. Powerline and ground can be reversed. Said test device comprises at least of a current mirror, having at least two branches. Each of said branches have at least one end. One end of the first branch is connected to said supply line at a first connection point. One end of the second branch is connected to said supply line at a second connection point. Said first and second connection point are located at a substantially different location of said supply line. Said current mirror is adapted for generating an output current. Said output current is related to said supply current. From the generated output current conclusions about occurrences of defects in said electronic device under test are drawn.
A typical operation of a current mirror known in the art is to generate currents in said branches of said current mirror in such a way that said current are proportional to each others. In the invention said typical operation of a current mirror is not exploited. Indeed the current mirror generates a output current being related to the supply current, therefore no proportionality between the currents in said branches is found while such a supply current flows. Still the terminology current mirror can be exploited as the circuitry still matches the current mirror layout.
In a first embodiment of this first aspect of the invention the test device further comprises circuitry for generating an offset voltage being applied to a first node of a capacitive element and means for measuring the voltage on a second node of said capacitive element with respect to a reference voltage, said means generating an output voltage. Said capacitive element is charged by said output current. From the measured voltage on said second node of said capacitive element conclusions about occurrences of defects in said electronic device under test are drawn.
In a second embodiment of this first aspect of the invention said test device is integrated with said electronic device on one integrated circuit.
In a third embodiment of this first aspect of the invention said test device comprises means for feeding said output voltage outside said one integrated circuit.
In a fourth embodiment of this first aspect of the invention said output voltage could also be combined with built-in self test circuitry, scan circuitry or boundary scan circuitry such that not necessary an additional output is required.
In a fifth embodiment of this first aspect of the invention said test device is adapted for testing a CMOS electronic device.
In a sixth embodiment of this first aspect of the invention said test device is adapted for testing an analog electronic device.
In a seventh embodiment of the invention said supply current is transient (dynamic).
In an eight embodiment of the invention said supply current is quiescent.
In a ninth embodiment of the invention said test device comprises means for discharging said capacitive element. Said means can be a switch.
In a tenth embodiment of the invention said reference voltage, exploited for the comparison, can either be applied from an external source using a

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