Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Patent
1993-06-24
1994-07-19
Nguyen, Vinh
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
324 731, 371 223, G01R 3102
Patent
active
053312740
ABSTRACT:
Both the input/output connections (16) of a circuit board (10) and the boundary scan devices (12.sub.1 -12.sub.n) thereon can be tested simultaneously by boundary scan techniques using a Serial Test Extension Module (STEM) (28) which mates with the circuit board. The STEM (28) contains at least one boundary scan register (36) which makes an electrical connection with a separate circuit board input/output connection (16) when the STEM mates with the board. The boundary scan registers (36) within the STEM (28) are serially connected in a chain, that is, connected in series with a chain of serially connected boundary scan registers (20) within the boundary scan devices (12.sub.1 -12.sub.n). By launching a known bit stream into the chain of boundary scan registers (20) and (36) and thereafter shifting out the bits and comparing them to a reference bit stream, representing a defect-free condition, faults in the input/output connections (16) and/or in the devices (12.sub.1 -12.sub.n) can be detected.
REFERENCES:
patent: 3854125 (1974-12-01), Ehling et al.
patent: 4707833 (1987-11-01), Tamaru
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 4963824 (1990-10-01), Hsieh et al.
patent: 4967142 (1990-10-01), Sauerwald et al.
patent: 5029166 (1991-07-01), Jarwala et al.
patent: 5056093 (1991-10-01), Whetrel
patent: 5115435 (1992-05-01), Langford, II et al.
patent: 5132635 (1992-07-01), Kennedy
patent: 5155732 (1992-10-01), Jarwala et al.
patent: 5173377 (1992-12-01), Robinson et al.
IEEE Standard Test Access Port and Boundary Scan Architecture, Chapter 1, May 21, 1990, IEEE, New York, N.Y.
IBM Technical Disclosure Bulletin, vol. 34, No. 10A, Mar. 1992, New York, N.Y., pp. 178-179, "I/O Logic Test."
Patent Abstracts of Japan, vol. 016, No. 060 (p. 1312)14, Feb. 1992, & JP-A-32 57 385 (Fujitsu), Nov. 15, 1991.
Microprocessor and Microsystems, vol. 15, No. 2, Mar. 1991, London GB, pp. 82-90, A. J. van de Goor et al., "A Low-Cost Tester for Boundary Scan."
Jarwala Najmi T.
Yau Chi W.
AT&T Bell Laboratories
Levy Robert B.
Nguyen Vinh
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