Method and apparatus for testing circuitry

Details Method and apparatus for testing circuitry Method and apparatus for testing circuitry

2001-07-27

2003-07-01

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06586959

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and apparatus for testing circuitry.
2. Discussion of the Related Art
When designing circuitry, it is necessary to test the circuitry before a design is finalised. For example, an integrated circuit may be tested.
FIG. 1
shows the principals involved in testing. The circuit under test
2
has an input signal
4
applied thereto. The circuit under test should provide certain output signals
6
in response to the input signal. For illustrative purposes only, the circuit under test is shown with one input signal and three output signals. These inputs and outputs may represent input and output pins respectively.
The circuit under test
2
introduces a delay into the signals. The output reference signal
6
a
is the same as the input reference signal
4
and effectively provides a measure of the delay caused by the circuit under test
2
. The delay introduced by the circuit under test
2
will vary from circuit to circuit. The other signals
6
b
and
6
c
output from the circuit under test
2
represent the response of parts of the circuit to the input reference signal
4
.
Reference is made to
FIGS. 2
a
-
2
d
which shows the input reference signal
4
and each of the output signals
6
a
-
6
c
. As can be seen from a comparison of
FIGS. 2
a
and
2
b
, the circuit under test
2
introduces a delay of Td to signals that pass therethrough.
In the process of testing, a series of equations is determined. An equation is defined for each input and output pin. In practice, a series of equations would be written for each pin so as to define the behaviour of the pin over time. These signals are defined with respect to the input signal. For example, the output reference signal
6
a
might be defined by the following equations: Td−xns and Td+xns. In the example shown, at Td−x ns, the output reference signal should be 0 and at time Td+xns, the output signal should be 1. In a similar way, equations are defined for the two other output signals
6
b
and
6
c
. Any references above or hereinafter to ns denote nanoseconds.
In practice, once the equations had been written for every single pin, the delay Td, that is the difference between the reference in signal
4
and the reference out signal
6
a
was measured. All of the equations that included the value Td were then updated with the measured value of Td. As Td varies from circuit to circuit, each time a circuit is tested, Td would have to be updated. The updating involved in these equations is very expensive in terms of test time. This is because virtually every pin in every wave set needs to be updated. For example, in one integrated circuit that was tested, approximately 20,000 cells of the wave set memory were evaluated and updated for the AC parametrics for each supply voltage.
It is an aim of embodiments of the present invention to address this problem.
SUMMARY OF THE INVENTION
According to embodiments of the present invention there is provided a method of testing a circuit comprising the steps of applying at least one input reference signal to a circuit under test; providing a reference signal from at least one output of said circuit under test; and defining at least one output signal of said circuit with reference to said reference output signal, wherein the timing of said output reference signal is defined independently of said input reference signal.


REFERENCES:
patent: 5578938 (1996-11-01), Kazami
patent: 5633879 (1997-05-01), Potts et al.
patent: 5675274 (1997-10-01), Kobayashi et al.
patent: 6281698 (2001-08-01), Sugimoto et al.
patent: 6347287 (2002-02-01), Beckett et al.
patent: 6356096 (2002-03-01), Takagi et al.
Standard Search Report from application No. 105566 completed on Jan. 17, 2001.
British Search Report from corresponding United Kingdom patent application 0019279.9, filed Aug. 4, 2000.

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