Method and apparatus for testing circuit boards

Details Method and apparatus for testing circuit boards Method and apparatus for testing circuit boards

1989-05-31

1991-07-02

Ruggiero, Joseph

Excavating

371 223, 371 225, G06F 1100

Patent

active

050291661

ABSTRACT:
A test system (10) is associated with a chain of circuits (12) on a circuit board (13) for testing the interconnections (11) linking the circuits in the chain as well as for testing the interconnections linking them to those on other boards. The test system includes a controller (22) for generating a test signal and for capturing a response signal generated by the associated chain of circuits in response to the test signal. The controller (22) also generates a flow control signal which controls a network (24) that routes the test signals from the controller, or from a first other test system, to the associated chain of circuits (12). In accordance with the flow control signal, the network (24) also serves to route the response signal from the associated chain of circuits (12) to the controller (22) or to a second other test system. By selectively routing the test and response signals, the network (24) in each test system (10) allows individual testing of each associated chain of circuits or, alternatively, permits the chains of circuits on several boards to be effectively interconnected for testing.

REFERENCES:
patent: 3772595 (1973-11-01), DeWolf
patent: 4055801 (1977-10-01), Pike
patent: 4397021 (1983-08-01), Lloyd
patent: 4402055 (1983-08-01), Lloyd
patent: 4716564 (1987-12-01), Hung
patent: 4727545 (1988-02-01), Glackemeyer
C. Gloster, "Boundry Scan With Built-In Self-Test", IEEE Design & Test, 2/1989, pp. 36-44.
R. Van Riessen, "An Architecture With Boundary Scan", IEEE Design & Test, 2/1990, pp. 9-19.
L. Whetsel, "A Standard Test Bus & Boundry Scan Architecture", TI Tech. Journal, Jul.-Aug./1988, pp. 48-59.
"Boundary-Scan Technique Targets Board-Level Testability", Computer Design, 10/1987, pp. 47 & 49.
"Testing and Diagnosis of Interconnects Using Boundary Scan Architecture", A. Hassa J. Rajski, and V. K. Agarwal, IEEE 1988 International Test Conference, Paper 7.1 pp. 126-137 (1988).
"Interconnect Testing with Boundary Scan", P. T. Wagner, IEEE 1987 International Test Conference, Paper 2.2, pp. 52-57 (1987).
"Electronic Chip-In-Place Test", P. Goel and M. T. McMahon, 1982 IEEE Test Conference, Paper 3.6, pp. 83-89 (1982).
"JTAG Boundry Scan Architecture Standard Proposal," Version 2.0, Joint Test Action Group, Mar. 30, 1988.
P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987, p. 66.

Affiliated with

Also associated with

Rating

Method and apparatus for testing circuit boards does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for testing circuit boards, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing circuit boards will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1253393