Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-12-23
2004-02-17
Deb, Anjan K. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010, C324S765010, C326S016000, C714S731000
Reexamination Certificate
active
06693436
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of integrated circuit testing and, more particularly, to testing of integrated circuits that provide one or more output-to-output relative signals.
2. Discussion of Related Art
The features and capabilities of integrated circuit testers can be important in determining the quality of the integrated circuits tested and can have a significant impact on their cost of manufacturing. A tester that is not capable of testing particular integrated circuit features may pass integrated circuit devices that do not operate properly, while a tester that does not provide an acceptable accuracy level may fail integrated circuit devices that perform as intended.
Source synchronous bus signaling techniques are being used more widely in recent years. In a source synchronous bus transaction, a transmitting device provides an output bus data signal along with an output strobe signal. A receiving device uses the output strobe signal to latch the bus data. Thus, source synchronous bus signaling falls under the general classification of output-relative, or output-to-output, timing specifications in which the timing of one or more output signals is specified relative to one or more different output signals.
Many currently available testers for very large scale integration (VLSI) circuits include timing systems that are based on a master clock within the tester. All timing edges driven to a device under test (DUT) and the timing of output compare signals within the tester are programmed relative to the tester's internal time base. For this reason, prior testers are not able to natively receive and test source synchronous signals.
To address this issue, one approach has been to perform a programmatic, iterative timing edge search for the source synchronous strobe signal from a DUT. Tester compare timings that are used to observe bus signals may then be recalculated based on the detected strobe edge. In this approach, once a strobe placement is determined, the same strobe placement is used for each subsequent bus cycle.
This process, however, is time consuming and, thus, expensive, such that it may not be viable for use in high volume manufacturing. Further, the above approach does not take into account the fact that strobe timing may vary with each bus cycle. Where the compare timing for the bus signals is set relative to an assumed fixed strobe timing, certain bus specifications may be tested too loosely or too tightly.
Further, as bus speeds continue to increase, the variation on bus output timing and limitations on tester edge placement accuracy will make it increasingly difficult to find any particular “sweet spot” at which to place a tester strobe to observe a DUT's source synchronous output response. Additionally, the tester strobe signal's edge placement accuracy becomes a larger portion of the bus cycle time such that it may become difficult to test certain timing specifications without producing an excessive number of false failures (i.e. yield loss).
In some cases, due to the above issues, cost reduction pressures may lead to eliminating testing of source synchronous or other output-relative AC timing specifications. Where such testing is not performed, however, the quality of integrated circuits may be compromised because integrated circuits that do not meet these timing specifications may not be identified during testing.
Thus, it is desirable to have an approach to testing source synchronous and other output-to-output relative output signals that may be more viable for high volume manufacturing.
SUMMARY OF THE INVENTION
A method and apparatus for testing an integrated circuit having an output-to-output relative signal are described.
In accordance with one embodiment, an apparatus for testing an integrated circuit comprises an output-relative signal receiver to receive an output-relative data signal and a corresponding output strobe signal from an integrated circuit device. The output-relative signal receiver is to produce a test strobe signal derived from the output strobe signal wherein the test strobe signal is to be used to test a feature of the integrated circuit device indicated by the output-relative data signal.
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Deb Anjan K.
Faatz Cynthia T.
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