Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2003-05-20
2004-08-17
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S007000
Reexamination Certificate
active
06777252
ABSTRACT:
TECHNICAL FIELD
This invention relates to the fabrication of optical chips and optical integrated circuits. More particularly, the invention relates to the testing of optical semiconductor chips while still in the wafer.
BACKGROUND OF THE INVENTION
Optical integrated circuits are fabricated on semiconductor chips. In the fabrication process, numerous chips are created on a wafer, generally a circular disk of some semiconductor material. The wafer comprises an array of individual chips
101
, demarcated by cleave marks
110
, as shown in FIG.
1
. Light enters and leaves each chip from its edge(s), where the direction of light is in the plane of the wafer. Thus, the regions on an individual chip where light enters and exits the chip, i.e. its edge(s), are obstructed by the neighboring chip(s) while a chip is still uncleaved and in the wafer. Therefore, conventionally, edge-emitting or edge-coupled chips must be first cleaved and facet-coated before they can be optically probed for testing. If the chip does not work, then the cleaving and facet-coating steps represent lost effort.
Such lost effort is not trivial in any sense. Commonly a certain proportion of chips on a wafer are faulty in some way, and do not operate, or do not operate according to required specifications. The proportion of chips that do operate satisfactorily is usually referred to as the yield. There is an inverse relationship between the yield and the wasted effort of cleaving and testing substandard chips. Yields less than 0.5 being common in numerous fabrication processes for simple optical devices, and even substantially lower yields when complex optical integrated circuit chips are being fabricated, what is needed is a method and apparatus that allows optical testing of a chip without requiring that the chip be first cleaved and facet coated.
SUMMARY OF THE INVENTION
A method of efficiently testing optical chips while still on the wafer is presented. One or more gutters for each chip on the wafer is provided, and either (1) a test signal is applied to the gutter to generate a response from the chip; or (2) a test signal is applied to the chip to generate a response from the gutter, where the gutter is in optical communication with the chip, and can reflect light incident or outgoing light at substantially a ninety degree angle.
REFERENCES:
patent: 4188123 (1980-02-01), Kleinknecht
patent: 5485540 (1996-01-01), Eda
Alphion Corporation
Everhart Caridad
Kaplan & Gilman LLP
Lee Calvin
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