Method and apparatus for testing a smallest addressable unit of

Details Method and apparatus for testing a smallest addressable unit of Method and apparatus for testing a smallest addressable unit of

1991-04-15

1994-03-08

Baker, Stephen M.

Excavating

371 213, 371 401, G06F 1100, G06F 1122, G11C 2900

Patent

active

052933830

ABSTRACT:
Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order. The test of a smallest addressable unit of a storage medium occurs completely and quickly in an optimum manner. To this end, a test procedure based on parity formation using at least first and second test patterns is used, wherein the effect of a bit error for a test pattern is transferred into the next test pattern. A combination of bit errors when checking this test pattern is thus recognized, derived from the addition of bit errors that appeared separately in the first and second test patterns.

REFERENCES:
patent: 4782487 (1988-11-01), Smelser
patent: 4980888 (1990-12-01), Bruce et al.

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