Method and apparatus for testing a multi-processor system

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3408255, 364200, G06F 1100

Patent

active

048021644

ABSTRACT:
A testing method and apparatus for a multi-processor system including a plurality of processors and a plurality of peripheral devices such as input/output (I/O) devices are disclosed. The processors can parallely access specified I/O devices. The apparatus comprises a plurality of I/O control tables each coupled to each of the I/O devices, and storing status information of the (I/O) device, and a scheduler for controlling accessing between the plurality of processors and the plurality of I/O devices. A lock control flag indicating whether each of the I/O devices is locked by one of the processors or not, is set in the respective I/O control table. The scheduler arbitrarily selects a processor which is accessible to an unaccessed I/O device on the basis of the state of the lock control flag of the I/O control table, each time of starting of the I/O device. Then, each time of starting of the I/O device. Then, a test program is executed, for the selected I/O device accessed by the selected processor, repeatedly with respect to different combinations of the I/O devices and the processors.

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