Method and apparatus for testing a logic circuit using parallel

Details Method and apparatus for testing a logic circuit using parallel Method and apparatus for testing a logic circuit using parallel

1980-07-23

1985-11-12

Strecker, Gerard R.

Electricity: measuring and testing

Plural, automatically sequential tests

364550, 371 15, G01R 1512

Patent

active

045530904

ABSTRACT:
A system for testing a logic circuit having a plurality of flip-flops associated with a scanning path between scanning-in and scanning-out terminals thereof and a combination circuit including logic gates is disclosed. In the system, parallel input data is transformed to serial data by a shift register, and the serial data is set in the flip-flops, while serial output data is transformed to parallel data by the shift register. The data is then output in parallel.

REFERENCES:
patent: 3621387 (1971-11-01), Smith et al.
patent: 3651315 (1972-03-01), Collins
patent: 3832535 (1974-08-01), DeVito
Tatah et al., "Level Sensitive Logic Testing", IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3680-3681.

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