Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2008-01-30
2011-12-06
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C714S029000, C714S033000, C714S047300, C714S734000, C714SE11021
Reexamination Certificate
active
08073668
ABSTRACT:
A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.
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Kellington Jeffrey William
Kudva Prabhakar Nandavar
Sanda Naoko Pia
Schumann John Andrew
Frejd Russell
International Business Machines - Corporation
Kahler Mark P
Talpis Matt
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