Method and apparatus for testing a circuit with reduced test pat

Details Method and apparatus for testing a circuit with reduced test pat Method and apparatus for testing a circuit with reduced test pat

1996-07-01

1998-04-14

Nguyen, Hoa T.

Excavating

371 221, 371 222, 3241581, G01R 3128

Patent

active

057401829

ABSTRACT:
A method and structure for testing a circuit with reduced test pattern generation constraints. The circuit includes a first logic circuit coupled to receive input signals from a first flip-flop and a second flip-flop. The first and second flip-flops store part of a test pattern generated to test the circuit. The circuit also includes first and second three state driver (TSD) circuits coupled to receive output signals from the first logic circuit. The output leads of the first and second TSDs are connected to a single input lead of a second logic circuit. The first and second TSDs receive control signals that enable and disable the first and second TSDs. The control signals are provided by the first logic circuit or, alternatively, by a separate decoder. During test operations, the control signals enable the first and second TSDs substantially simultaneously for a predetermined duration. The predetermined duration is short enough to prevent burnout of the first and second TSDs when outputting signals of different logic levels. The predetermined duration is long enough to allow the test pattern to propagate through the second logic circuit and load the output signals of the second logic circuit into third and fourth flip-flops.

REFERENCES:
patent: 5363383 (1994-11-01), Nimishakavi
patent: 5406567 (1995-04-01), Ogawa
patent: 5642362 (1997-06-01), Savir

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