Method and apparatus for test generation and fault simulation fo

Details Method and apparatus for test generation and fault simulation fo Method and apparatus for test generation and fault simulation fo

1994-05-31

1996-03-12

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

054992494

ABSTRACT:
Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.

REFERENCES:
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4769817 (1988-09-01), Krohn et al.
patent: 5036473 (1991-07-01), Butts et al.
C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. CAD, vol. CAD-6, pp. 148-151, Sep. 1986.
Y. K. Malaiya and R. Narayanaswamy, "Modeling and Testing for Timing Faults in Synchronous Sequential Circuits," IEEE Design and Test of Comput., vol. 1, pp. 62-74, Nov. 1984.
G. L. Smith, "Model for Delay Faults Based upon Paths," Proc. Int'l Test Conf., pp. 342-349, 1985.
S. Davedas, "Delay Test Generation for Synchronous Sequential Circuits," Proc. Int'l Test Conf., pp. 144-152, Sep. 1989.
Chakraborty et al., "Delay Fault Models & Test Generation for Random Logic Sequential Circuits," 1992, pp. 165-172, IEEE Design Automation Conf.
Agrawal et al., "Generating Tests for Delay Faults in Nonscan Circuits," 1993, pp. 20-28, IEEE Design & Test of Computers.
Chakraborty et al., "On Behavior Fault Modeling for Combinational Digital Designs," 1988, pp. 593-600, IEEE Int'l Test Conf.
Chakraborty et al., "Path Delay Fault Simulation Algorithms for Sequential Circuits," 1992, pp. 52-56, IEEE 1992.
Hill et al., "A Vector Based Backward State Justification Search for Test Generation in Sequential Circuits," pp. 630-637, IEEE 1990.
Cheng, "The Back Algorithm for Sequential Test Generation," pp. 66-69, IEEE 1988, Int'l Conf. on Computer Design.
Cheng et al., "GENTEST: An Automatic Test Generation System for Sequential Circuits," Apr. 1989, pp. 13-18, IEEE Computer.
Hill, "Interlocked Test Generation & Digital Hardware Synthesis," 1991, pp. 52-56, IEEE.
Lee et al., "A New Test Generation Method for Sequential Circuits," 1991, pp. 446-449.
Bollinger et al., "An Investigation of Circuit Partitioning for Parallel Test Generation," IEEE VLSI Test Symposium 1992, pp. 119-124.

Affiliated with

Also associated with

Rating

Method and apparatus for test generation and fault simulation fo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for test generation and fault simulation fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for test generation and fault simulation fo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2105884