Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Temperature
Reexamination Certificate
2000-01-07
2004-07-13
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Temperature
C257S536000, C257S537000, C257S538000, C257S904000
Reexamination Certificate
active
06762474
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic circuits and, more particularly, to temperature compensation of read-only-memory (ROM) electronic circuits.
BACKGROUND OF THE INVENTION
Read-Only Memories (ROMS) are well known in the art. Typically, ROMs are used in computer systems to provide a permanent storage of program instructions, such as mathematical functions, or informational data that is processed by mathematical functions. As is known in the art, a ROM typically consists of a planar array of parallel word lines, which are perpendicular to and insulated from a planar array of parallel bit lines. In one embodiment of a ROM device, the two planes containing the word lines and bit lines are vertically disposed from each other and separated by an insulating layer. Active semiconductor devices such as bi-polar transistors or metal oxide semiconductor field effect transistors (MOSFETs) interconnect the junction of each word line and each bit line to form a memory cell. Typically, in the fabrication process, and for economy of scale, all the cells are populated with devices, and then a link to a particular device is opened in the encoding process to render that cell inactive. The connection or lack of connection of a device at a memory cell determines whether a logic “1” or “0” is stored in the cell. The control electrode (base or gate) of the active device is connected to the word line, and the emitter or source electrode is typically connected to the bit line, for transistor or MOSFET devices, respectively. A positive potential on a word line turns “on” the device at that cell. Where there is no physical link at the cell there is no signal transmitted to the bit line. The bit lines are then read in parallel to obtain a group of“1” and “0” signals that form the output of the ROM.
ROM devices may also be fabricated with resistive interconnections. U.S. Pat. No. 5,847,442 to Mills, et al., entitled “Structure for Read-Only Memories,” which is incorporated by reference herein teaches a ROM device fabricated using resistive devices to interconnect word and bit lines. The use of resistive devices is advantageous over transistor devices as resistive devices are easier to fabricate and smaller in size. A brief summary of the incorporated reference is presented to provide a better understanding of the invention claimed herein.
A ROM device fabricated with resistive devices is illustrated in
FIG. 1
of the referred to U.S. Patent and is repeated herein as FIG.
1
. In the device shown, only certain word lines
28
are connected to bit lines
40
by resistive device
30
. The connection between word line
28
and bit line
40
is specified by the specific data stored in the ROM device. Resistive device
30
is formed as a column, or post, within the insulating material that separates parallel word line
28
from the vertically disposed parallel bit line
40
.
Resistive device
30
may be fabricated within a wide range of values. In order to reduce cross-talk between word line
28
and bit line
40
the minimum value of resistance is in the order of tens of Megaohms. To achieve resistive values in the order of tens of Megaohms in the space allocated, resistive device
30
is typically comprised of a polysilicon material having a controlled resistivity. Polysilicon materials are well known in the art and, as is known, may be formulated in a doped or undoped condition. Doping elements are typically selected from a group of elements consisting of boron, phosphorous, arsenic, and antimony. As discussed in the referenced patent, a significant advantage of using a polysilicon post as a resistor device to interconnect word and bits lines is a decrease in the size of a memory cell as resistive devices are smaller and required less power than transistors or MOSFETs.
However, polysilicon is highly temperature sensitive, and, as is known in the art, the resistance of polysilicon decreases significantly with an increase in temperature. As the temperature increases and the resistivity of the connecting polysilicon resistive device decreases, the current through the resistive device increases. The increased current is known in the art to adversely affect the output voltage of the ROM as the output voltage is directly related to the current. One method of compensating for the increased output voltage is also disclosed in the aforementioned U.S. Patent. This method discloses using an operational amplifier with a gain characteristic responsive to the change in temperature as sense amplifier
42
. As disclosed, the operational amplifier employs a feedback resistor with electrical and thermal characteristics similar to those of data resistor
30
. In this method, the gain of the operational amplifier decreases as the resistance of the feedback resistor decreases. The decreased gain compensates for the increased data current and maintains the output voltage substantially constant.
However, a disadvantage of this method of compensation is that the current flowing through the ROM device remains strongly related to the change in temperature. This change in current flow further affects the switching speed of the ROM device, and accordingly, the switching speed remains strongly influenced by the change in temperature.
SUMMARY OF THE INVENTION
The present invention relates to temperature compensation of Read-Only Memory (ROM) that uses a temperature sensitive resistive material to connect word and bit lines. In such devices, the change in temperature adversely affects the output voltage and the switching speed of the ROM.
In accordance with the invention, the current through a data resistive device is maintained at a substantially constant level by supplying to the ROM an input reference voltage that is responsive to changes in temperature. In one embodiment of the invention, an input reference voltage is developed by supplying a constant current source across a temperature-dependent reference resistor. The resistance of a reference resistor changes in response to changes in temperature and the voltage across the reference resistor (and input to the ROM) changes accordingly. By changing the input voltage in response to a change in temperature, the data current to the ROM data resistors remains substantially constant. With a substantially constant current flow through the ROM device, the output voltage and ROM switching speed are maintained substantially constant.
In an exemplary embodiment of the invention, the reference resistor is made from a material that has a similar temperature-dependent resistivity as the material selected as the resistive device that interconnects word and bit lines within the ROM. In this embodiment of the invention, a change in resistance of the reference resistor matches a change in resistance of the data resistor, thus causing the current flow through the data resistor to remain substantially constant for any change in temperature.
REFERENCES:
patent: 4727269 (1988-02-01), Luich
patent: 5047655 (1991-09-01), Chambost et al.
patent: 5394343 (1995-02-01), Tsao
patent: 5544000 (1996-08-01), Suzuki et al.
patent: 5548252 (1996-08-01), Watanabe et al.
patent: 5585741 (1996-12-01), Jordan
patent: 5627457 (1997-05-01), Ishiyama et al.
patent: 5729154 (1998-03-01), Taguchi et al.
patent: 5847442 (1998-12-01), Mills, Jr. et al.
patent: 5859458 (1999-01-01), Hsueh et al.
patent: 5881014 (1999-03-01), Ooishi
patent: 6028472 (2000-02-01), Nagumo
patent: 2071501 (1971-09-01), None
Agere Systems Inc.
Warren Matthew E.
Wilson Allan R.
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