Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-29
2001-07-03
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S146000, C710S023000, C711S148000
Reexamination Certificate
active
06255869
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to integrated circuitry in which a common resource is shared by multiple domains. In particular, the invention relates to chips having a memory resource shared by two processor domains.
BACKGROUND OF THE INVENTION
Integrated circuitry incorporates and interconnects numerous electronic components. These electronic components may perform numerous functions and interact in complex ways. Some electronic components, referred to herein as “resources”, are shared by one or more other components (“domains”), e.g., a digital signal processor (“DSP”). The resource is shared in that it may communicate with or serve numerous domains, albeit only one domain at any point in time. If two or more electronic domains were to attempt to use the shared resource simultaneously, data might be corrupted.
This gives rise to the concept of resource negotiation. Resource negotiation techniques are well known in chip design. Resource negotiation is performed to determine which domain is permitted to use the shared resource at a particular point in time in the event of conflict.
One common type of resource negotiation circuit uses a four-state state machine. For example, a chip may comprise two digital signal processor cores, DSP
1
and DSP
2
which share a common memory resource, such as a block of SRAM. A four-state state machine may be used in which the four states are represented by binary numbers 00, 01, 10, and 11, wherein state 00 indicates that neither DSP
1
nor DSP
2
is permitted to use the resource, i.e., neither “owns” the resource, 01 means that DSP
1
owns the resource, 10 means that DSP
2
owns the resource, and 11 is an inoperative state. The use of a four-state state machine is common because of the binary basis of digital logic, i.e., four states because four is a power of two. However, this leads to one inoperative state which tends to slow the resource negotiation circuit because the state machine must be “stepped” through the inoperative state to reach an operative state. Typically, the state machine is configured such that the inoperative state falls back to one of the other three operable states.
Also, the state machine is a “single clock edge” state machine, that is, it is configured to react on only one edge of each clock cycle, e.g., on the rising edge of the clock. If DSP
1
and DSP
2
issue sequential but nearly simultaneous requests, DSP
1
's request may be clocked into a resource negotiation circuit on the rising edge of the reference clock and DSP
2
's request may be delayed, after release of the resource by DSP
1
, while waiting for the next edge, e.g., rising edge, that controls the state machine. Delay, such as that caused while waiting for a next edge, is undesirable, particularly in high speed applications.
Additionally, a considerable amount of chip space is required to implement a single clock edge synchronous four-state resource negotiation circuit. Chip space is precious and more compact circuitry requiring less chip space is desirable, particularly in increasingly popular system-on-a-chip (SOC) designs.
SUMMARY OF THE INVENTION
The invention provides a method and apparatus for negotiating access to a shared resource by two independent domains. A request register is provided to each domain for receiving an ownership request signal. Request signals received from both domains are clock-synchronized and fed to a cross-coupled circuit.
The cross-coupled circuit includes two blocks, each having a switch and a register for receiving a request signal. The registers are responsive to different portions of a clock cycle, e.g., rising and falling edges. The switch in each block receives a signal from one domain on one input and a signal from the output of the register in the same block on the other input. The switch of one block is controlled by the output signal of the register of the other block.
The output of one of the blocks is used to control a domain switch to permit data streams from the independent domains to reach the shared resource.
Each domain requests use of the shared resource by sending a request signal to its respective request register. The cross-coupled circuit negotiates ownership and controls the domain switch. Simultaneous requests are time-separated due to the clock-phase based nature of the cross-coupled circuit.
REFERENCES:
patent: 5394557 (1995-02-01), Ellis
patent: 5692216 (1997-11-01), Wolford et al.
patent: 6055594 (2000-04-01), Lo et al.
Agere Systems Guardian Corp.
Lam Tuan T.
Synnestvedt & Lechner LLP
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