Excavating
Patent
1990-04-12
1992-11-03
Beausoliel, Robert W.
Excavating
364267, 3642674, 364DIG1, 371 205, G06F 1100
Patent
active
051611627
ABSTRACT:
A workstation or server having a central processing unit (CPU) and a standard system bus interface and loopback control logic. The I/O subsystem is tested through the application of diagnositc programs running in the CPU which use programmed I/O bus cycles to read and write from the standard system bus interface. In this way, the CPU, with the loopback test mode enabled, can functionally test data paths and controls utilized to perform programmed I/O accesses to the standard system bus interface without having to access an external system bus device. Furthermore, a loopback bus cycle can cause a direct virtual memory access (DVMA) bus cycle to be created at the system bus interface. Therefore, the CPU, with the loopback test mode enabled, can also functionally test data paths and controls utilized to perform system memory DVMA without the presence of an external system bus device.
REFERENCES:
patent: 4575792 (1986-03-01), Keeley
patent: 4730313 (1988-03-01), Stephenson
patent: 4858234 (1989-08-01), Hartwell
patent: 4972345 (1990-11-01), Munier
"Bidirectional Interface Test Circuit", IBM TDB, vol. 28, No. 3, Aug. 1985, pp. 1073-1074.
Chang Hugh
Michels Kurt
Van Loo William C.
Watkins John
Beausoliel Robert W.
Sun Microsystems Inc.
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