Method and apparatus for synchronous clock distribution to a...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S149000, C713S375000, C713S400000, C713S500000, C713S600000

Reexamination Certificate

active

07619449

ABSTRACT:
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.

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Zilic, Zeljko, “Phase- and Delay-Locked Loop Clock Control in Digital Systems,” EDA Design Line <<http://www.edadesignline.com/showArticle.jhtml;jsessionid=EJAGCES43SIKIQSNDLPSK...>>Aug. 17, 2001, 4 pages.
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