Method and apparatus for synchronous circuit simulation design b

Details Method and apparatus for synchronous circuit simulation design b Method and apparatus for synchronous circuit simulation design b

1997-05-12

1999-11-02

Eng, David Y.

G06F 9455

Patent

active

059785713

ABSTRACT:
A method for use in the design or implementation of a synchronous circuit having nodes interconnecting logic functions and in which the nodes assume logic values in successive clocked phases of a logical cycle. For a phase for a node connected to an output of a logic function, a determination is made (and stored) of which nodes, connected to inputs of the logic function, have and do not have timing behaviors in that phase which are needed in order to determine the logic value assumed by the output node in that phase.

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F. Hirose; Performance Evaluation of an Event-Driven Logic Simulation Machine; Jun. 12, 1992; 29th ACM/IEEE Design Automation Conf.; pp. 428-431.
M. Saitoh; Logic Simulation System Using Simulation Processor (SP) 1988; 25th ACM/IEEE Design Automation Conf.; pp. 225-230.

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