Method and apparatus for synchronizing timing signals of two int

Details Method and apparatus for synchronizing timing signals of two int Method and apparatus for synchronizing timing signals of two int

1995-05-30

1997-05-20

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 12, 327159, 327149, 327244, H03K 513, H03K 500

Patent

active

056315910

ABSTRACT:
A phase synchronization circuit uses a phase comparator and adjustable delay lines that selectively delay a system clock timing signal applied to two integrated circuit chips. The phase comparator and delay lines compensate for propagation delays in each of the integrated circuit chip. The phase comparator receives bus clock signals of the two chips and generates two trigger signals for application to two counters. The counters count signals are applied to corresponding delay lines, which are clocked by a system clock. The delayed timing signals from the delay lines furnish timing signals to the corresponding integrated circuit chips. The count of the counter which corresponds to the integrated circuit chip having the smaller propagation delay is increased until the bus clock signals for the two integrated circuit chips are phase synchronized.

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