Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1998-11-20
2001-02-06
Phan, Trong (Department: 2818)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06184813
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electrical circuits, and, more particularly, to synchronizing the arrival times of signals at an output terminal in electrical circuits. Still more particularly, the present invention relates to synchronizing the arrival times of signals at an output terminal in a digital to analog converter.
2. Description of the Related Art
Electrical components such as resistors, capacitors, inductors, and transistors are routinely implemented in electrical circuits. The type of electrical component utilized in an electrical circuit will depend on the particular implementation. Designers typically weigh the advantages and disadvantages of each type of electrical component before selecting the desired component. For example, an electrical circuit implemented in silicon can employ a variety of resistors, such as poly-crystalline silicon or diffusion-type resistors (hereinafter referred to as “diffusion” resistors). While poly-crystalline silicon and/or diffusion resistors serve their intended purpose of providing adequate resistance in an electrical circuit, such resistors have a tendency to sometimes introduce undesirable electrical characteristics such as parasitic capacitance.
The parasitic capacitance of the poly-crystalline silicon, diffusion, or other resistors tends to introduce undesirable signal-propagation delays in electrical circuits, thereby preventing the signals from arriving at their intended destination in proper synchronism. Because of propagation delays, signals arriving late at their intended destination, such as an output terminal, for instance, may contribute to higher levels of noise at the output terminal. The undesirable effects caused by the parasitic capacitance of resistors can be illustrated with reference to a digital-to-analog (D/A) converter
100
shown in FIG.
1
.
For clarity, only a portion of the D/A converter
100
that is necessary to illustrate the undesirable effects caused by the parasitic capacitance is shown in FIG.
1
. Specifically,
FIG. 1
illustrates a simplified block diagram of an n-bit R
2
R D/A converter
100
, which is constructed using diffusion resistors
110
. Although the R
2
R D/A converter
100
is illustrated having diffusion resistors
110
, it is should be apparent to those skilled in the art that other types of resistors may also be employed in the R
2
R D/A converter
100
.
The D/A converter
100
includes a plurality of latches
120
(
a-n
) that activate a corresponding plurality of switches
130
(
a-n
) in response to receiving a synchronization signal on a line
140
. The number of latches
120
(
a-n
) and switches
130
(
a-n
) required in a particular implementation may vary, depending on the number of bits that are converted by the D/A converter
100
in response to each synchronization signal on the line
140
. For example, in one embodiment, converting
16
bits may require sixteen latches
120
(
a-n
) and switches
130
(
a-n
) (where “a” equals 1 and “n” equals 16). The synchronization signal on the line
140
in the illustrated embodiment is a strobe signal that is substantially simultaneously provided to the latches
120
(
a-n
). The latches
120
(
a-n
) store respective bit signals on lines
150
(
a-n
) that are provided by an interpolator (not shown). The latches
120
(
a-n
) provide the bit signals to the respective plurality of switches
130
(
a-n
) in response to the strobe signal on the line
140
. The switches
130
(
a-n
) connect either to a ground or non-ground node
155
,
160
when the latches
120
(
a-n
) are strobed by the strobe signal on the line
140
, depending on the value of the bit signal stored in the latches
120
(
a-n
).
In the illustrated embodiment, a first latch
120
a
and a last latch
120
n
of the plurality of latches
120
(
a-n
) are adapted to receive the least significant bit (LSB) and most significant bit (MSB), respectively. Accordingly, although not shown, the intermediate latches
120
(
c
to
n−
1) between the first and last latches
120
a
,
120
n
are adapted to receive the respective intermediate bit signals.
Because of the parasitic capacitance associated with the diffusion resistors
110
, the least significant bit applied to the first latch
120
a
suffers the longest delay from the moment it is strobed-in until it reaches an output node
192
of the D/A converter
100
. On the other hand, the most significant bit, when applied to the last latch
120
n
, which is closest to the output node
192
, reaches the output node
192
with minimum delay. The mismatch in the arrival times due to the parasitic capacitance of the diffusion resistors
110
results in an undesirable spike (not shown) at the output node
192
.
The size of the spike is a function of the unit parasitic capacitance, as well as the digital code applied. That is, a larger unit of capacitance means a longer delay, and, hence, a wider spike for a given digital code. Moreover, a more significant code transition (i.e., where n switches from 31 to 32 binary digits, as opposed to switching from 15 to 16 bits) may also result in a wider and higher spike. Such spikes generally tend to adversely affect the signal-to-distortion (STD) ratio of a signal at the output node
192
.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for synchronizing the arrival of data delivered over a first and second path. The method includes generating a first clock signal; delivering the data to the first path in response to receiving the first clock signal; delaying the first clock signal by a preselected time, wherein the first preselected time substantially corresponds to a difference in the time required for the data to propagate the first and second paths; and delivering the data to the second path in response to receiving the delayed clock signal.
In another aspect of the instant invention, an apparatus is provided that includes a first and second storing device, and a clock generator. The first storing device includes an input terminal and a strobe input terminal, the first storing device capable of providing data from the input terminal and delivering the data to a first path in response to a first strobe signal. The second storing device includes an input terminal and a strobe input terminal, the second storing device capable of providing data from the input terminal and delivering the data to a second path in response to a second strobe signal. The clock generator is capable of providing a first clock signal to the strobe input terminal of the first storing device and capable of providing a second strobe signal to the strobe input terminal of the second storing device, wherein the second strobe signal is provided a preselected time after the first strobe signal and wherein the first preselected time substantially corresponds to a difference in the time required for the data to propagate the first and second paths.
REFERENCES:
patent: 4335445 (1982-06-01), Nercessian
patent: 4801923 (1989-01-01), Schwartz et al.
patent: 5274376 (1993-12-01), Phillips et al.
patent: 5585802 (1996-12-01), Cabler et al.
patent: 5900830 (1999-05-01), Scheffler
Abughazaleh Firas N.
Nair Vijayakumaran V.
Legerity Inc.
Phan Trong
Williams Morgan & Amerson P.C.
LandOfFree
Method and apparatus for synchronizing signals does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for synchronizing signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for synchronizing signals will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2560793