Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-11-15
2002-07-09
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C713S400000
Reexamination Certificate
active
06418526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to parallel processing systems, and in particular a method and system for configuring a massively parallel processing system.
2. Description of the Related Art
Parallel processing is considered an advantageous approach for increasing processing speeds in computer systems. Parallel processing can provide powerful communications and computer systems which can handle complex problems and manipulate large databases quickly and reliably.
One example of parallel processing can be found in U.S. Pat. No. 4,412,285, issued Oct. 25, 1983, to Neches et al., incorporated by reference herein. This patent describes a system using a sorting network to intercouple multiple processors so as to distribute priority messages to all processors. Another example of parallel processing can be found in U.S. Pat. No. 5,321,813 issued Jun. 14, 1994 to McMillen et al., which reference is also hereby incorporated by reference herein.
One of the difficulties associated with parallel processing systems involves the logical configuration of such systems. Prior art parallel processing systems are typically configured with the use of five inter-dependent services for: (1) registering nodes, (2) examining local and global net states, (3) merging global parallel processing info with local info, (4) freezing the selected parallel processing configuration, and (5) selecting or dropping parallel processing nodes. On very large systems, these methods can be unreliable. Further, in some cases, use of these methods can render some of the drivers and interfaces of the massively parallel processing system unusable.
From the foregoing, it can be seen that there is a need for a simplified method for logically configuring a parallel processing systems. The present invention satisfies this need.
SUMMARY OF THE INVENTION
To address the requirements described above, the present invention discloses a simplified method, apparatus, and article of manufacture for synchronizing nodes in a parallel processing system.
The method comprises the steps of receiving a registration request from each of the non-coordinator nodes in the coordinator node and, after a registration request has been received from all of the non-coordinator nodes, sending a wakeup message from the coordinator node to each of the non-coordinator nodes to wake the non-coordinator nodes from a sleep state. In another embodiment of the invention, the method comprises the steps of transmitting a registration request from a non-coordinator node to a coordinator node; commanding the non-coordinator node to enter a sleep state; receiving a multicast wakeup message from the coordinator node in the non-coordinator node after a registration request is received from all of the non-coordinator nodes in the coordinator node; and waking the non-coordinator node in response to the wakeup message.
The apparatus comprises a means for performing the steps described above, and the article of manufacture comprises a program storage device tangibly embodying computer instructions for performing the above method steps.
Using the steps outlined above, this definition and use of the coordinator node use of the above invention allows a parallel processing system to be configured with fewer operations and fewer configuration services than possible in the prior art. Specifically, the number of configuration services to be reduced from five to two (one for selecting the coordinator, and the second for configuring the parallel processing system), simplifying software and hardware design, and improving maintainability and reliability as well.
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Denman Robert W.
Merritt John E.
Follansbee John A.
Gates & Cooper
NCR Corporation
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