Method and apparatus for synchronizing multiple clocks

Details Method and apparatus for synchronizing multiple clocks Method and apparatus for synchronizing multiple clocks

1997-02-18

1998-04-21

Heckler, Thomas M.

G06F 112

Patent

active

057427992

ABSTRACT:
A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.

REFERENCES:
patent: 4785469 (1988-11-01), Joshi et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5410263 (1995-04-01), Waizman
patent: 5450458 (1995-09-01), Price et al.
"A Dual PLL Based Multi Frequency Clock Distibution Scheme," Albert Thaik and Hai Ngoc Nguyen, IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 84-85, 1992.
"A Variable Delay Line PLL for CPU-Coprocessor Synchronization," Mark G. Johnson and Edwin L. Hudson, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.

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