Method and apparatus for synchronizing data queues in asymmetric

Details Method and apparatus for synchronizing data queues in asymmetric Method and apparatus for synchronizing data queues in asymmetric

1994-10-20

1996-12-24

Chan, Eddie P.

395468, 39520008, 395874, 395881, 395489, G06F 1314

Patent

active

055881327

ABSTRACT:
A network of processors synchronize modification of a common data structure stored in an asymmetric reflective memory by using a queue. A first processor stores a queue element in a global write-only address space of the reflective memory, the reflective memory to copy the queue element to a local read/write address space of a second processor. The first processor also stores a queue header in the global write-only address space. In response to detecting the queue element, the second processor reads the queue header and then overwrites the queue header with a zero. The reading and writing of the queue header are performed atomically in the local read/write address space of the second processor. The second processor processes the queue element, and marks the queue element as processed in the global address space of the reflective memory.

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