Pulse or digital communications – Synchronizers
Reexamination Certificate
2005-08-17
2009-12-29
Perilla, Jason M. (Department: 2611)
Pulse or digital communications
Synchronizers
C375S355000
Reexamination Certificate
active
07639764
ABSTRACT:
The present invention provides method and apparatus for synchronizing data between different clock domains in a memory controller. In one embodiment, a memory controller is provided that includes a command decoder and synchronizing logic. The command decoder is operable to receive a command in accordance with a first clock domain. The synchronizing logic synchronizes the command to a second clock domain that is different from the first clock domain, and includes a first synchronization flop and a second synchronization flop operable to prevent metastability associated with synchronizing the command to the second clock domain.
REFERENCES:
patent: 4851710 (1989-07-01), Grivna
patent: 4949361 (1990-08-01), Jackson
patent: 5155745 (1992-10-01), Sugawara et al.
patent: 5256912 (1993-10-01), Rios
patent: 5379401 (1995-01-01), Robinson et al.
patent: 5388248 (1995-02-01), Robinson et al.
patent: 5422855 (1995-06-01), Eslick et al.
patent: 5548620 (1996-08-01), Rogers
patent: 5638015 (1997-06-01), Gujral et al.
patent: 5857005 (1999-01-01), Buckenmaier
patent: 6009496 (1999-12-01), Tsai
patent: 6055285 (2000-04-01), Alston
patent: 6128678 (2000-10-01), Masteller
patent: 6154788 (2000-11-01), Robinson et al.
patent: 6157967 (2000-12-01), Horst et al.
patent: 6260152 (2001-07-01), Cole et al.
patent: 6308229 (2001-10-01), Masteller
patent: 6359479 (2002-03-01), Oprescu
patent: 6434684 (2002-08-01), Manning
patent: 6584540 (2003-06-01), Shinmori
patent: 6714612 (2004-03-01), Chaudry
patent: 6738917 (2004-05-01), Hummel et al.
patent: 6754765 (2004-06-01), Chang et al.
patent: 6778436 (2004-08-01), Piau et al.
patent: 6848060 (2005-01-01), Cook et al.
patent: 7058799 (2006-06-01), Johnson
patent: 7219250 (2007-05-01), Abendroth et al.
patent: 7242737 (2007-07-01), Lake et al.
patent: 7352836 (2008-04-01), Mendenhall
patent: 7366938 (2008-04-01), Warren et al.
patent: 2003/0067814 (2003-04-01), Piau et al.
patent: 2003/0079077 (2003-04-01), Piau et al.
patent: 2003/0131185 (2003-07-01), Dover
patent: 2003/0169644 (2003-09-01), Liao
patent: 2003/0210603 (2003-11-01), Ong
patent: 2004/0049627 (2004-03-01), Piau et al.
patent: 2005/0280455 (2005-12-01), Hutson
patent: 2006/0036888 (2006-02-01), Warren et al.
patent: 2006/0098770 (2006-05-01), Harper et al.
patent: 2006/0168423 (2006-07-01), Nolan et al.
patent: 2006/0277329 (2006-12-01), Paulson et al.
patent: WO-2007022368 (2007-02-01), None
patent: WO-2007022368 (2007-02-01), None
Smith, Scott F., et al., “Low-latency Multiple Clock Domain Interfacing Without Alteration of Local Clocks”,Proceedings, IEEE 15th Biennial University/Government/Industry Microelectronics Symposium(UGIM '03), [online]. [archived Jan. 22, 2007]. Retrieved from the Internet: <http://web.archive.org/web/20070122062851/http://coen.boisestate.edu/ssmith/coen/UGIM03.pdf>, (Jun. 30 - Jul. 2, 2003), 342-343.
Atmel Corporation
Perilla Jason M.
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Method and apparatus for synchronizing data between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for synchronizing data between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for synchronizing data between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4077334