Method and apparatus for synchronizing a plurality of output clo

Details Method and apparatus for synchronizing a plurality of output clo Method and apparatus for synchronizing a plurality of output clo

1996-12-26

1999-03-23

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Diverging with single input and plural outputs

327 99, 327154, 327161, 327404, H03K 1762

Patent

active

058865624

ABSTRACT:
A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

REFERENCES:
patent: 5124572 (1992-06-01), Mason et al.
patent: 5306962 (1994-04-01), Lamb
patent: 5450084 (1995-09-01), Mercer
patent: 5519666 (1996-05-01), McAdams
patent: 5532633 (1996-07-01), Kawai
Research Disclosure, No. 295, Kenneth Mason Publications Ltd, England. Nov. 1988.
R. Gregorian et al., "Analog MOS Integrated Circuits for Signal Processing", A vol. in the Wiley Series on Filters: Design, Manufacturing and Applications; A Wiley Interscience Publication, 1986, pp. 516-517.

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