Boots – shoes – and leggings
Patent
1993-12-29
1995-07-18
Ramirez, Ellis B.
Boots, shoes, and leggings
375354, 371 161, 371 162, 371 221, 371 223, 371 226, G05B 2302, G06F 1127, H04L 700
Patent
active
054348048
ABSTRACT:
A microprocessor is provided with circuitry for receiving JTAG and ICE test control signals through JTAG test ports and for synchronizing the test signals to a chip clock signal. Test signals synchronized to an external JTAG device are processed internally by an ICE of the microprocessor chip once the test signals are synchronized with the chip clock rate. To this end, the microprocessor is provided with a synchronizer which receives the chip clock signal, a JTAG control signal, and a JTAG reset signal, and outputs a synchronized control signal. The synchronizer includes an unclocked SR flip-flop for sampling the JTAG control signal, and two or more DR flip-flops for synchronizing the JTAG control signal to the chip clock signal. The synchronizer may be configured to generate a control signal pulse or a control signal level. The synchronizer is protocol independent, i.e., the clock rate of the JTAG test commands is independent of the chip clock. Hence, no protocol is required to connect the JTAG test command signals to the ICE. In particular, the synchronizer includes an input stage configured for allowing the JTAG control signal to be much slower than the core clock signal or much faster than the core clock signal.
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Alexander James W.
Bock Robert
Assouad Patrick J.
Intel Corporation
Ramirez Ellis B.
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