Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1981-10-23
1984-08-07
Griffin, Robert L.
Pulse or digital communications
Spread spectrum
Direct sequence
375118, 328109, H04L 704
Patent
active
044647697
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method and apparatus for synchronizing a binary data signal coming to a receiver having a locally available.
The binary data signal can be of the so-called RZ type (return to zero) or of the so-called NRZ type (non-return to zero).
BACKGROUND ART
The synchronizing problem is always present in all data transmission, and is solved depending on the application, demand on accuracy etc. in different ways. For example, if the Transmitter and Receiver side clocks are synchronized, possibly against a common reference, the detection of data at the Receiver side does not cause any problems of course. Synchronizing of a Receiver clock can be in a mode such that the timing information is extracted from the transmitted data signal, e.g. by time determination of its zero crossings, subsequent to which a signal corresponding to the timing information is allowed to actuate a controllable local clock signal generator. Requirements in respect to transient time and permitted error in the data transmission naturally affects the selection of the synchronizing method also.
DISCLOSURE OF INVENTION
The technical problem in the present case lies in correctly detecting, with the aid of a signal which is asynchronus to the data signal, of a message sent to the receiver, with the condition that the addition or fall-away of a binary character in the message has no effect. This condition is fulfilled in a redundant system, for example, in which the same message of a fixed number of bits is sent repeatedly in succession and the receiver accepts the message on condition that it can detect the same message a given number of times during a given time. If the addition or fall-away of a binary character in the data signal occurs relatively rarely, such an occassional happening would thus not effect the receiver's correct detection of the message.
The clock signal being asynchronous must naturally not signify that there is a too great frequency deviation from the correct value. A frequency deviation in the order of magnitude of one per thousand gives rise, in accordance with the invention, to addition or fall-away of information in approximately every thousandth bit position, which can be accepted in many applications.
The solution of this problem proposed by the present invention is characterized in the appended patent claims. The first advantage with an apparatus in accordance with the invention is its extreme simplicity and meagre power requirement.
BRIEF DESCRIPTION OF DRAWINGS
The invention will now be described with the aid of some embodiments with reference to the appended drawing on which
FIG. 1 is a block diagram of an apparatus in accordance with the invention,
FIG. 2 is a phase-reversing circuit incorporated in the apparatus according to FIG. 1,
FIG. 3 is a first sampling circuit incorporated in the apparatus according to FIG. 1,
FIG. 4 illustrates the time sequence for a plurality of signals in the apparatus according to FIG. 1, and
FIG. 5 illustrates the same signals as in FIG. 4, for another embodiment.
BEST MODE OF CARRYING OUT THE INVENTION
FIG. 1 is a block diagram of an apparatus in accordance with the invention. Between a data input 4 and a data output 6 there is a first sampling circuit 1 and a second sampling circuit 2 coupled in series. A phase-reversing circuit (or phase inverter) 3 is connected between a clock input 5 and the clock signal input on the first sampling circuit 1. The second sampling circuit 2 is clocked directly from the clock input 5.
The data signal transmitted from the transmitter side is applied to the data input 4, and this signal is assumed to be a binary coded signal of the RZ or NRZ type, according to what has been mentioned above. The data signal is sampled with the aid of the clock signal on the clock input 5, the clock signal being asynchronous relative the data signal, according to the assumptions, to give on the data output a signal synchronous with the clock signal and corresponding to the input data signal.
The phase-reversing
REFERENCES:
patent: 3631463 (1971-12-01), Murphy
patent: 3697881 (1972-10-01), Nakagome et al.
patent: 3936602 (1976-02-01), Korver
patent: 4010323 (1977-03-01), Peck
patent: 4128828 (1978-12-01), Samejima et al.
patent: 4208724 (1980-06-01), Rattlingourd
Forsberg Gunnar S.
Ingre Lars P.
Chin Stephen
Griffin Robert L.
Telefonaktiebolaget L M Ericsson
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