Method and apparatus for synchronized clock distribution

Details Method and apparatus for synchronized clock distribution Method and apparatus for synchronized clock distribution

1998-07-13

2000-05-02

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

329565, H03K 104

Patent

active

06057724&

ABSTRACT:
A method and apparatus are described which eliminate the clock skew problems associated with routing clock signals throughout a circuit. Particularly well suited for Very Large Scale Integration ("VLSI") chips, the method and apparatus provide a resonator which is distributed across the circuit. This allows the clock to be accessed at a variety of locations without any propagation delay between the access points. The method for distributing a single, distributed clock signal to a plurality of clock connection points in a circuit comprises two steps. The first step is to generate the clock signal, such that the clock signal is available at a plurality of clock source points without propagation delay. The second step is to couple the plurality of clock source points to the plurality of clock connection points in the circuit.

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patent: 5296748 (1994-03-01), Wicklund et al.
patent: 5517532 (1996-05-01), Reymond
patent: 5519351 (1996-05-01), Matsumoto
patent: 5640112 (1997-06-01), Goto et al.
patent: 5691662 (1997-11-01), Soboleski et al.
Circuits, Interconnections and Packaging for VLSI, by H.B. Bakuglu, Chapter 1, System-Level Performance Optimization, pp. 14 and 15.

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