Method and apparatus for synchronization of row and column...

Details Method and apparatus for synchronization of row and column... Method and apparatus for synchronization of row and column...

2005-03-29

2005-03-29

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06873568

ABSTRACT:
A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.

REFERENCES:
patent: 5694369 (1997-12-01), Abe
patent: 6269050 (2001-07-01), Kwon et al.
patent: 6339553 (2002-01-01), Kuge
patent: 6590829 (2003-07-01), Takeuchi
patent: 6639869 (2003-10-01), Toda et al.
patent: 0278155 (1988-08-01), None
patent: 2000163966 (2000-06-01), None

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