Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-05-04
2002-08-06
Ton, Dang (Department: 2661)
Multiplex communications
Pathfinding or routing
Through a circuit switch
Reexamination Certificate
active
06430180
ABSTRACT:
TECHNICAL FIELD OF INVENTION
The present invention refers to a method and an apparatus for switching data between a set of input bitstreams and a set of output bitstreams in a circuit switched time division multiplexed network, each of said bitstreams being divided into recurring frames and each of said frames being divided into time slots.
TECHNICAL BACKGROUND AND PRIOR ART
Today, new types of circuit switched communication networks are being developed for the transfer of information using time division multiplexed bitstreams, wherein the bitstreams of the network are divided into recurrent, typically fixed size frames, each frame in turn being divided into time slots.
An example of such a network, referred to as a DTH (Dynamic synchronous Transfer Mode) network, is described in “The DTM Gigabit Network”, Christer Bohm, Per Lindgren, Lars Ramfelt, and Peter Sjödin, Journal of High Speed Networks, 3(2):109-126, 1994, and in “Multi-gigabit networking based on DTM”, Lars Gauffin, Lars Håkansson, and Björn Pehrson, Computer networks and ISDN Systems, 24(2):119-139, April 1992.
In such a network, so called switch nodes, each connected to at least two bitstreams, are used to switch time slot data between different bitstreams, more specifically between time slot positions on different bitstreams. If, for example, a circuit (or “channel”) is defined by a first set of time slot positions on a first bitstream and a second set of time slot positions on a second bitstream, a switch node is typically used to transfer or copy time slot data from the first set of time slot positions to the second set of time slot positions.
According to prior art, switches in circuit switched time division multiplexed networks use control memories that map incoming slot positions to outgoing slot positions. Such mapping may involve both a mapping in the time domain, i.e. control of the order in which time slot data are written into each bitstream, and a mapping in the space domain, i.e. controlling which time slot data goes to which bitstream. For general background, so-called time-space-time (TST) switches are described in “Data and Computer Communications”, 4
th
ed., by Williams Stallings, Macmillan Publishing Company.
As an example of prior art switches, U.S. Pat. No. 4,005,272 (Collins et al.), describes a switch apparatus wherein incoming bitstream frames are stored in respective inlet memories and wherein outgoing bitstream frames are stored in respective outlet memories. Based upon information provided in a plurality of control memories, time slot data stored in said inlet memories are transferred to said outlet memories via a space switch. A first control memory is used to designate the inlet memory entry that is currently connected to the space switch, thereby providing a time switching function at the inlet port. Another control memory is used to designate the outlet memory entry that is currently connected to the space switch, thereby correspondingly providing a time switching function at the outlet port. Also, further control memories are provided to control which cross-connections that are to be made over within the space switch.
A disadvantage of switch nodes of the above mentioned kinds is that they do not allow arbitrary communication between input and output ports, i.e. they show limitation as to the possibilities of arbitrary switching time slots in space and time, which consequently also limits switching speed and capacity. Because of the operation features of a space switch of the kind used in, e.g., U.S. Pat. No. 4,005,272, any-to-any switching is typically rendered impossible. In most cases, a first selection of mapping of a specific input time slot position to a specific output time slot position will directly imply restrictions as to a second selection of further mapping. This of course also limits the possibilities of providing space and time multicasting and/or broadcasting.
Furthermore, in prior art, input and output ports are connected together using a shared medium that handles the aggregated switching capacity of the input ports to not provide blocking. This typically requires switch internal processing at a bit rate of several times the bit rate of the network bitstreams, which of course limits the scalability of such a design.
OBJECTS OF THE INVENTION
An object of the invention is to provide a switching apparatus and method that provides greater freedom as to the possibilities of arbitrarily switching time slots in space and time.
Another object of the invention is to provide a solution that efficiently handles time and space multicasting and broadcasting channels.
Another object of the invention is to provide a simple and fast mechanism for switching between multiple incoming and outgoing bitstreams which are arbitrarily phase shifted.
Another object of the invention is to increase the general switching speed and capacity.
Yet another object of the invention is to provide a scaleable switching system, wherein smaller switches may easily be integrated into forming larger switches.
SUMMARY OF THE INVENTION
The above mentioned and other objects are achieved by the invention as defined in the accompanying claims.
According to the invention, there is provided a method and an apparatus for switching data between a set of input bitstreams and a set of output bitstreams in a circuit switched time division multiplexed network, each of said bitstreams being divided into recurring frames and each of said frames being divided into time slots. The input bitstreams are received and the frames thereof are temporarily stored in a set of memory means (for simplicity referred to below as a set of frame buffers). Each frame buffer is used for temporarily storing frames of a respective bitstream of said input bitstreams. For each frame of each one of said output bitstreams and in sequence accordance with the order that said time slot data is to be transmitted therein, time slot data is selectively read from frames temporarily stored in said set of frame buffers. Said time slot data, as selectively read from said frame buffers, are then transmitted into allocated time slots of said output bitstreams.
Consequently, in a switch embodying the invention, each input port is associated with a respective frame buffer for temporary storing of frames that are received at said input port. All output ports can, independently of one another, read data from any one or more of said frame buffers in a non-blocking manner. A full switch thus comprises a set of frame buffers, each being arranged in a 1-to-many (one input to many outputs) fashion.
According to the invention, time and space switching is advantageously accomplished in one single integrated step by the selective reading of data from the frames that are stored in said set of frame buffers, only requiring one single read control function (for example implemented using a so called slot mapping table) for controlling said selective reading for each output bitstream.
Furthermore, as each input bitstream is written into a respective frame buffer, and time slot data for the output bitstreams are read out from said frame buffers as requested for output, a switch according to the invention will only have to be able to operate at a rate essentially corresponding to the bitstream bit-rate. However, this does not prevent the invention from being used in relation to memory means operating at a bit-rate exceeding wire speed.
Also, using the invention, no multiplexing of time slots from different bitstreams is needed at the input side (or corresponding demultiplexing at the output side) of the memory means, in contrast to what is often encountered in prior art.
According to a preferred embodiment of the invention, said frame buffers are realized by means of multiported random access memories (RAM), which allows insertion and retrieval to be performed independently and without phase synchronization.
By using RAMs with multiple read ports, each output bitstream will, independently of others, retrieve its own time slot data and preferably collect it using lines pri
Bohm Christer
Gauffin Lars
Holm Lukas
Roos Joachim
Net Insight AB
Ton Dang
LandOfFree
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