Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-05-20
2001-03-20
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000
Reexamination Certificate
active
06204721
ABSTRACT:
BACKGROUND
1. Field of Invention
This invention relates generally to PMOS semiconductor memories and specifically to adjusting well potential levels in response to changes in output voltage levels.
2. Description of Related Art
FIG. 1
shows a, PMOS negative charge pump
10
having four diode-capacitor stages each including an MOS capacitor C and a diode-connected PMOS transistor D. The diode-connected transistors have a threshold voltage VT equal to, for instance, 0.7 volts. Odd numbered stages are driven by a clock signal CLK. Even numbered stages are driven by the complementary clock signal {overscore (CLK)}. Clock signals CLK and {overscore (CLK)} swing between ground potential and a positive voltage V
CLK
equal to, for instance, a supply voltage V
DD
of about 3 volts.
The negative charge pump
10
is typically formed in one or more n− well regions of a p− substrate.
FIG. 2
shows the negative charge pump
10
formed in a single n− well region
11
of a p− substrate
12
. The p+ diffusion regions
13
-
18
serve as the source/drain regions of the PMOS diode-connected transistors D
0
-D
4
, where the p+ source region
13
of the first diode D
0
is coupled to ground potential and the p+ drain region
18
of the last diode D
4
is coupled to the output terminal OUT of the negative charge pump
10
. A p+ diffusion region
19
serves as the p+ contact for the n− well region
11
and is coupled to a welltap terminal WT.
During operation of the negative charge pump
10
, the p− substrate
12
is grounded and the n− well region
11
is held at the supply voltage V
DD
, thereby preventing the p
junction therebetween from forward biasing. Initially, the clock signal CLK is low (at ground potential) and its complement signal {overscore (CLK)} is high (at V
DD
). The threshold voltage V
T
of the first stage diode Do forces associated node N
1
to one diode-drop |V
T
| above ground potential, i.e., to about 0.7 volts. The first capacitor C
1
is thus charged to about 3 volts with respect to ground potential. On the next clock cycle, clock signal {overscore (CLK)} transitions low to ground potential and pushes node N
1
to a voltage equal to |V
T
|−V
CLK
=0.7−3=−2.3 volts. The second stage node N
2
is driven to one diode drop above node N
1
, i.e., to about −1.6 volts (ideally). Since the clock signal CLK is at V
CLK
=3 volts, there is about a −4.6 volt drop across the capacitor C
2
(ideally). On the following clock cycle, clock signal CLK transitions to ground potential and pushes node N
2
from −1.6 volts to −3 volts (ideally). Operation continues as described above, until node N
4
, and thus the output terminal OUT, are driven to a high negative voltage. Note that the output terminal OUT (i.e., p+ region
18
) is a diode drop |V
T
| more positive than is node N4 (i.e., p+ region
17
).
In some applications, such as when providing erase voltages to a PMOS floating gate memory cell of the type disclosed in U.S. Pat. No. 5,687,118, a negative potential of −11 volts or more is required. The maximum negative voltage of the output terminal OUT is given by:
V
OUT
(MAX)=
V
BD
−V
DD
−V
T
where, V
BD
is the breakdown voltage of the p+ region
17
− well region
11
junction and V
T
is the threshold voltage of PMOS diode D
4
. Since the breakdown voltage V
BD
is typically about −11 volts, and assuming V
DD
=3 volts and V
T
=−1 volts, the output terminal OUT of the pump
10
is limited to about −8 volts.
In addition, as the voltage differential between the p+region
17
and the n− well region
11
increases, so does the threshold voltage V
T
of the PMOS diode-connected transistors D of the negative charge pump
10
. Since the threshold voltage V
T
limits the amount by which each stage of the negative charge pump
10
may pull down its output voltage, efficiency of the negative charge pump
10
is also compromised by the increase in V
T
(in the negative direction) due to a higher back bias between each of the p+ regions
14
-
18
and the n− well region
11
.
SUMMARY
A switching circuit is disclosed which switches the well potential of a semiconductor circuit in response to changes in the output voltage of that circuit. A switching circuit in accordance with the present invention includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.
REFERENCES:
patent: 5243236 (1993-09-01), McDaniel
patent: 5338978 (1994-08-01), Larsen et al.
patent: 5371419 (1994-12-01), Sundby
patent: 5396128 (1995-03-01), Dunning et al.
patent: 5553295 (1996-09-01), Pantelakis et al.
patent: 5914632 (1999-06-01), Fotouhi et al.
Nguyen Chinh D.
Yuen Guy S.
Callahan Timothy P.
Nguyen Hai L.
Paradice III William L.
Programmable Microelectronics Corp.
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