Multiplex communications – Diagnostic testing – Fault detection
Reexamination Certificate
1998-09-24
2003-09-09
Kizou, Hassan (Department: 2662)
Multiplex communications
Diagnostic testing
Fault detection
C370S241000, C370S243000, C370S244000, C370S246000, C370S250000, C375S356000, C375S357000, C375S359000, C379S001010
Reexamination Certificate
active
06618358
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to automatic selection of a T1/E1 transmission line for use as a data clock source.
BACKGROUND OF THE INVENTION
An internet Network Access Server (NAS) provides dial-up services to users over multiple T1/E1 transmission lines in a Public Services Telephone Network (PSTN). A user dials into the access server in order to be connected to the internet.
The access server transmits and receives data through the public telephone service over the T1/E1 transmission lines. Each T1/E1 line is clocked by a telephone switching system in the PSTN. The data is clocked internally to various modules within the access server where the data is analyzed and routed. If an independent operating clock inside the access server is used to clock the data within the access server, then the internal clock will likely be out of phase with the incoming data. In order to synchronize the data with the internal access server clock, the data must be buffered resulting in additional hardware requirements for the access server.
Internal buffering can be avoided by using a recovered clock extracted from an incoming T1/E1 line to drive the internal data bus of the access server. This allows the data to be clocked internally at the same speed as the incoming data thus negating the need for additional buffering hardware.
Where there are multiple T1/E1 lines coming into the access server, it is necessary to select one of the T1/E1 clock lines to use as the source for internal clocking inside the access server.
An example of a conventional device for switching between two T1/E1 clock lines is shown in
FIG. 1. A
T1 line terminates on each of line interface controllers
10
and
20
. Each line interface controller recovers a clock signal CLK from the incoming data on the corresponding T1 line. Each line interface controller also generates a Loss-of-Signal (LOS) alarm LOS which becomes active when the line interface controller detects loss of the incoming analog signal. LOS typically becomes active after 100 contiguous zeros are received. An example of a line interface controller is the BT8370 from Rockwell.
The recovered clock signal from line interface
10
is input to demultiplexor (DMUX)
34
of clock selection controller
30
as the primary clock PRI. The recovered clock signal from line interface
20
is input to DMUX
34
as the secondary clock SEC. DMUX
34
also receives an oscillator signal OSC which provides a free running clock signal which is not synchronized to either the primary or secondary T1 lines. DMUX
34
selects one of the primary PRI, secondary SEC or free running oscillator OSC inputs for output as a SELECTED CLK signal under control of a SELECTION CONTROL signal. The SELECTED CLK can be input to a data switch, such as a time division multiplexed (TDM) switch, for use as a data transfer clock. The MT90820 from Mitel is an example of a TDM switch.
The SELECTION CONTROL signal is generated by automatic/manual state machine
32
of clock selection controller
30
. The automatic/manual state machine
32
receives LOS
1
from line interface controller
10
and LOS
2
from line interface controller
20
. The automatic/manual state machine
32
also receives a MANUAL SELECT input signal by which a user can determine whether the state machine operates in either manual or automatic mode. When in manual mode, the user, by way of commands input via a RSEL input, can select the primary PRI or secondary SEC clock sources and the automatic/manual state machine
32
will generate the SELECTION CONTROL signal accordingly. The user can also select the free run OSC clock source by inputting a particular value for the MANUAL SELECT input signal.
In the automatic mode, the automatic/manual state machine
32
selects the primary PRI, secondary SEC or free run OSC clock sources based upon the state of the LOS
1
and LOS
2
signals. Normally, if LOS
1
is inactive, then the state machine will select the primary clock source PRI and generate the SELECTION CONTROL signal accordingly so that the recovered clock signal obtained from the T1 line terminating on line interface controller
10
is switched through DMUX
34
to the SELECTED CLK output. However, if LOS
1
becomes active, then line interface controller
10
has lost the T1 signal and, responsive thereto, the state machine selects the secondary clock source SEC recovered by line interface controller
20
for output as the SELECTED CLK. If LOS
1
and LOS
2
are both active, line interface controllers
10
and
20
have both lost their T1 signals. The state machine
32
will then switch to the free running OSC clock source.
When either of the loss-of-signals LOS
1
and LOS
2
clear, then the state machine
32
detects the change of status on the T1 line and switches to the primary clock source PRI, if LOS
1
clears, or to the second clock source SEC, if LOS
2
clears but LOS
1
remains active. The primary PRI clock is given the highest priority for selection followed by the secondary SEC clock and, finally, the free running OSC clock.
The priority of the clock signals input to the clock selection controller
30
is determined by the physical connection to the clock selection controller
30
circuit. The clock recovered from the T1 line terminating on line interface controller
10
is always given higher priority for clock selection purposes than the clock recovered from the T1 line terminating on line interface controller
20
by virtue of their physical connections to the controller circuit
30
. Thus, the hardwired priority scheme of the T1 clocks are hardwired in the system of FIG.
1
and cannot be altered via user inputs except in the manual mode.
Also, the design of clock selection controller
30
only contemplates recovered clock signals from two T1 facilities. The explosion of demand for internet access has led to an increase in the bandwidth required by Network Access Servers (NAS) which is obtained by serving each NAS with a greater number of T1 facilities for data transfer.
Furthermore, the design of clock selection controller
30
can only monitor one alarm signal, LOS, for each T1 line. There are other T1 signals that can identify problems on a T1 line. Examples of other performance indicator signals are alarm-indication-signal (AIS), yellow alarm (YEL), lost frame alignment (FRED), excessive zeroes (EXZ), loss-of-frame (LOF), framing error (FERR), multi-frame error (MFERR) among others. Many of these alarm conditions can affect the quality of the clock signal recovered from the corresponding T1 facility. These performance monitoring signals for T1 lines are ignored in the controller of FIG.
1
.
The MT9042B multi-trunk system synchronizer from Mitel is an example of the conventional clock selection controller
30
shown in FIG.
1
.
Accordingly, a need remains for a clock selection controller that has increased failure detection capability and configurability and can also accommodate the increased number of T1 lines in NASs.
SUMMARY OF THE INVENTION
An embodiment of a clock selection controller, according to the present invention, has a plurality of clock inputs. Each one of the plurality of clock inputs is configured to receive a recovered clock signal from a line interface controller and a clock output configured to output an internal clock signal. The controller also has a first plurality of alarm inputs. Each one of the first plurality of alarm inputs corresponds to one of the plurality of clock inputs. Each one of the first plurality of alarm inputs are configured to receive a first alarm signal from the line interface controller providing the recovered clock signal to the corresponding one of the plurality of clock inputs. A user interface is configured to receive user configuration commands so that a user can determine a priority scheme among the plurality of clock inputs.
A clock signal switch is coupled to each of the plurality of clock inputs and the clock output. The clock signal switch is configured to receive a clock selection signal at a control input and switch the recovere
Dukkipati Venkaiah
Mahajan Sanjeev A.
Cisco Technology Inc.
Kizou Hassan
Logsdon Joe
Marger Johnson & McCollom PC
LandOfFree
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