Static information storage and retrieval – Floating gate – Particular connection
Patent
1997-09-24
1998-10-13
Nelms, David
Static information storage and retrieval
Floating gate
Particular connection
36518533, G11C 1134
Patent
active
058222448
ABSTRACT:
A flash memory (12) has a plurality of banks of memory cells (20, 22). If a read operation of the flash memory (12) is required to the same bank of memory cells in which a program/erase operation is being performed, the program/erase operation is automatically suspended while the read operation is performed. Also, a wait signal is asserted by the flash memory (12) to indicate to a processor (10) that the program/erase operation is being suspended. After the program/erase operation is suspended, the wait signal is negated. If multiple read operations are requested, all the read operations are performed before the program/erase operation resumes.
REFERENCES:
patent: 5034922 (1991-07-01), Burgess
patent: 5339279 (1994-08-01), Toms et al.
patent: 5341330 (1994-08-01), Wells et al.
patent: 5355464 (1994-10-01), Fandrich et al.
patent: 5648929 (1997-07-01), Miyamoto
patent: 5748972 (1998-05-01), Clark et al.
Advanced Micro Devices, Inc. 1997, "Simultaneous Read/Write Architecture", 3 pgs.
Advanced Micro Devices, Inc. 1997, Am29DL800T/Am29DL800B 8 Megabit (1 M.times.8-Bit/512 K.times.16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory, pp. 1-38.
Hansen John Phillip
Metzger Erik
Hill Daniel D.
Motorola Inc.
Nelms David
Phan Trong
LandOfFree
Method and apparatus for suspending a program/erase operation in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for suspending a program/erase operation in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for suspending a program/erase operation in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-320231