Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
2005-04-20
2008-12-02
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C712S237000
Reexamination Certificate
active
07461237
ABSTRACT:
A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.
REFERENCES:
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5623615 (1997-04-01), Salem et al.
patent: 5958040 (1999-09-01), Jouppi
patent: 6134649 (2000-10-01), Witt
Ali Abid
Caprioli Paul
Chaudhry Shailender
Lee Miles
Pan Daniel
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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